@database 2650UM.guide @author Signetics, Inc. @node Main "Signetics 2650 User Manual" @{" GENERAL FEATURES " link Gene} INTERNAL ORGANIZATION @{" INTERNAL REGISTERS " link Orga1} @{" PROGRAM STATUS WORD " link Orga2} @{" MEMORY ORGANIZATION " link Orga3} FEATURES @{" SUBROUTINE LINKAGE " link Feat1} @{" CONDITION CODE USAGE " link Feat2} INSTRUCTIONS @{" ADDRESSING MODES " link Inst1} @{" INSTRUCTION FORMATS " link Inst2} @{" C: ADDITIONAL INFORMATION " link AppC} D: INSTRUCTIONS @{" ALPHABETIC LISTING " link Alph} @{" NUMERIC LISTING " link Nume} @{" ORGANIZED BY FUNCTION " link Func} @{" E: SUMMARY OF 2650 INSTRUCTION MNEMONICS " link AppE} @{" F: NOTES ABOUT THE 2650 PROCESSOR " link AppF} @endnode @node Gene "GENERAL FEATURES" The 2650 processor is a general purpose, single chip, fixed instruction set, parallel 8-bit binary processor. A general purpose processor can perform any data manipulations through execution of a stored sequence of machine instructions. The processor has been designed to closely resemble conventional binary computers, but executes variable length instructions of one to three bytes in length. BCD arithmetic is made possible through use of a special @{"DAR" link DAR} machine instruction. The 2650 is manufactured using Signetics' N-channel silicon gate MOS technology. N-channel provides high carrier mobility for increased speed and also allows the use of a single 5-volt power supply. Silicon gate provides for better density and speed. Standard 40-pin dual in-line packages are used for the processor. The 2650 contains a total of seven general purpose registers, each eight bits long. They may be used as source or destination for arithmetic operations, as index registers, and for I/O transfers. The processor can address up to 32768 bytes of memory in four pages of 8192 bytes each. The processor instructions are one, two or three bytes long, depending on the instruction. Variable length instructions tend to conserve memory space since a one- or two-byte instruction may often be used rather than a three-byte instruction. The first byte of each instruction always specifies the operation to be performed and the addressing mode to be used. Most instructions use six of the first eight bits for this purpose, with the remaining two bits forming the register field. Some instructions use the full eight bits as an operation code. The most complex direct instruction is three bytes long and takes 9.6 microseconds to execute. This figure assumes that the processor is running at its maximum clock rate, and has an associated memory with cycle and access times of one microsecond or less. The fastest instruction executes in 4.8 microseconds. The clock input to the processor is a single phase pulse train and uses only one interface pin. It requires a normal TTL voltage swing, so no special clock driver is required. The Data Bus and Address signals are tri-state to provide convenience in system design. Memory and I/O interface signals are asynchronous so that Direct Memory Access (DMA) and multiprocessor operations are easy to implement. The 2650 has a versatile set of addressing modes used for locating operands for operations. They are described in detail @{"here" link Inst1}. The interrupt mechanism is implemented as a single level, address vectoring type. Address vectoring means that an interrupting device can force the processor to execute code at a device-determined location in memory. @endnode @node Orga1 "INTERNAL REGISTERS" In order for the processor to execute an instruction, it performs the following general steps: 1. The Instruction Address Register (IAR) provides an address for memory. 2. The first byte of an instruction is fetched from memory and stored in the Instruction Register (IR). 3. The Instruction Register (IR) is decoded to determine the type of instruction and the addressing mode. 4. If an operand from memory is required, the operand address is resolved and loaded in the Operand Address Register (OAR). 5. The operand is fetched from memory and the operation is executed. 6. The first byte of the next instruction is fetched. The Instruction Register (IR) holds the first byte of each instruction and directs the subsequent operations required to execute each instruction. The IR contents are decoded and used in conjunction with the timing information to control the activation and sequencing of all the other elements on the chip. The Holding Register (HR) is used in some multiple- byte instructions to contain further instruction information and partial absolute addresses. The Arithmetic Logic Unit (ALU) is used to perform all of the data manipulation operations, including Load, Store, Add, Subtract, And, Inclusive Or, Exclusive Or, Compare, Rotate, Increment and Decrement. It contains and controls the Carry (C) bit, the Overflow (OVF) bit, the Interdigit Carry (IDC) bit and the Condition Code (CC) register. The Register Stack (RS) contains six registers that are organized into two banks of three registers each. The Register Select (RS) bit picks one of the two banks to be accessed by instructions. In order to accommodate the register-to-register instructions, register zero (R0) is outside the array. Thus, register zero is always available along with one set of three registers. The Address Adder (AA) is used to increment the instruction address and to calculate relative and indexed addresses. The Instruction Address Register (IAR) holds the address of the next instruction byte to be accessed. The Operand Address Register (OAR) stores operand addresses and sometimes contains intermediate results during effective address calculations. The Return Address Stack (RAS) is an eight level, Last In, First Out (LIFO) storage which receives the return address whenever a Branch-to- Subroutine instruction is executed. When a Return instruction is executed, the RAS provides the last return address for the processor's IAR. The stack contains eight levels of storage so that subroutines may be nested up to eight levels deep. The Stack Pointer (SP) is a three-bit wraparound counter that indicates the next available level in the stack. It always points to the current address. @endnode @node Orga2 "PROGRAM STATUS WORD" The Program Status Word (PSW) is a special purpose register within the processor that contains status and control bits. It is 16 bits long and is divided into two bytes called the Program Status Upper (PSU) and the Program Status Lower (PSL). The PSW bits may be tested, loaded, stored, preset or cleared using the instructions which affect the PSW. The sense bit, however, cannot be set or cleared because it is directly connected to pin #1. +------+------+------+------+------+------+------+------+ PSU | S | F | II | Not used | SP2 | SP1 | SP0 | +------+------+------+------+------+------+------+------+ 7 6 5 4 3 2 1 0 S: Sense F: Flag II: Interrupt Inhibit SP2: Stack Pointer 2 SP1: Stack Pointer 1 SP0: Stack Pointer 0 +------+------+------+------+------+------+------+------+ PSL | CC1 | CC0 | IDC | RS | WC | OVF | COM | C | +------+------+------+------+------+------+------+------+ 7 6 5 4 3 2 1 0 CC1: Condition Code 1 CC0: Condition Code 0 IDC: Interdigit Carry RS: Register Bank Select WC: With/Without Carry OVF: Overflow COM: Logical/Arithmetic Compare C: Carry/Borrow SENSE (S) The Sense bit in the PSU reflects the logic state of the sense input to the processor at pin #1. The sense bit is not affected by the @{"LPSU" link LPSU}, @{"PPSU" link PPSU}, or @{"CPSU" link CPSU} instructions. When the PSU is tested (@{"TPSU" link TPSU}) or stored into register zero (@{"SPSU" link SPSU}), bit #7 reflects the state of the sense pin at the time of the instruction execution. FLAG (F) The Flag bit is a simple latch that drives the Flag output (pin #40) on the processor. INTERRUPT INHIBIT (II) When the Interrupt Inhibit (II) bit is set, the processor will not recognize an incoming interrupt. When interrupts are enabled (II=0), and an interrupt signal occurs, the inhibit bit in the PSU is then automatically set. When a @{"RETE" link RETE} instruction is executed, the inhibit bit is automatically cleared. STACK POINTER (SP) The three Stack Pointer bits are used to address locations in the Return Address Stack (RAS). The SP designates the stack level which contains the current return address. The three SP bits are organized as a binary counter which is automatically incremented with execution of Branch-to- Subroutine instructions, and decremented with execution of Return instructions. CONDITION CODE (CC) The Condition Code is a two-bit register which is set by the processor whenever a general purpose register is loaded or modified by the execution of an instruction. Additionally, the CC is set to reflect the relative value of two bytes whenever a compare instruction is executed. The following table indicates the setting of the CC whenever data is set into a general purpose register. The data byte is interpreted as an 8-bit, two's complement number. @{u}Register Contents CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 For compare instructions the following table summarizes the setting of the CC. The data is compared as two 8-bit absolute numbers if bit #1, the COM bit, of the Program Status Lower (PSL) byte is set to indicate "logical" compare (COM=1). If the COM bit indicates "arithmetic" (COM=0), the comparison instructions interpret the data bytes as two 8-bit two's complement binary numbers. Register to Storage Register to Register @{u}Compare Instruction Compare Instruction CC1 CC0@{uu} Reg X Greater than Storage Reg #0 Greater than Reg X 0 1 Reg X Equal to Storage Reg #0 Equal to Reg X 0 0 Reg X Less than Storage Reg #0 Less than Reg X 1 0 The CC is never set to %11 by normal processor operations, but it may be explicitly set to %11 through @{"LPSL" link LPSL} or @{"PPSL" link PPSL} instruction execution. INTERDIGIT CARRY (IDC) For BCD arithmetic operations it is sometimes essential to know if there was a carry from bit #3 to bit #4 during the execution of an arithmetic instruction. The IDC reflects the value of the Interdigit Carry from the previous add or subtract instruction. After any add or subtract instruction execution, the IDC contains the carry or borrow out of bit #3. The IDC is also set upon execution of Rotate instructions when the WC bit in the PSW is set. The IDC will reflect the same information as bit #5 of the operand register after the rotate is executed. REGISTER SELECT (RS) There are two banks of general purpose registers with three registers in each bank. The register select bit is used to specify which set of three general purpose registers will be currently used. Register zero is common and is always available to the program. An individual instruction may address only four registers, but the bank select feature effectively expands the available on-chip registers to seven. When the Register Select bit is 0, registers #1, #2 and #3 in register bank #0 will be accessible, and when the bit is 1, registers #1, #2 and #3 in register bank #1 will be accessible. WITH/WITHOUT CARRY (WC) This bit controls the execution of the add, the subtract and the rotate instructions. Whenever an add or a subtract instruction executes, the following bits are either set or cleared: Carry/Borrow (C), Overflow (OVF), and Interdigit Carry (IDC). These bits are set or reset without regard to the value of the WC bit. However, when WC=1, the final value of the carry bit affects the result of an add or subtract instruction, ie. the carry bit is either added (add instruction) or subtracted (subtract instruction) from the ALU. Whenever a rotate instruction executes with WC=0, only the eight bits of the rotated register are affected. However, when WC=1, the following bits are also affected: Carry/Borrow (C), Overflow (OVF) and Interdigit Carry (IDC). The carry/borrow bit is combined with the 8-bit register to make a nine-bit rotate. The overflow bit is set whenever the sign bit (bit #7) of the rotated register changes its value, ie. from a zero (0) to a one (1) or from a one (1) to a zero (0). The interdigit carry bit is set to the new value of bit #5 of the rotated register (!). OVERFLOW (OVF) The overflow bit is set during add or subtract instruction executions whenever the two initial operands have the same sign but the result has a different sign. Operands with different signs cannot cause overflow. For example: A binary +124 (%01111100) added to a binary +64 (%01000000) produces a result of %10111100 which is interpreted in two's complement form as a -68. The true answer would be 188, but that answer cannot be contained in the set of 8-bit, two's complement numbers used by the processor, so the OVF bit is set. Rotate instructions also cause OVF to be set whenever the sign of the rotated byte changes. +------------------------------------+ | +-----+ | | | IDC | (NOT CHANGED) | | +-----+ | +---+ | +------------------------------+ | | C | +--+ 7 < 6 < 5 < 4 < 3 < 2 < 1 < 0<--+ WC=0 +---+ +------------------------------+ ROTATE REGISTER LEFT WITHOUT CARRY +----------------------------------------------+ | +-----+ | | | IDC <-+ | | +-----+ | | | +---+ +-------------+----------------+ | +--+ C <-----+ 7 < 6 < 5 < 4 < 3 < 2 < 1 < 0<--+ WC=1 +---+ +------------------------------+ ROTATE REGISTER LEFT WITH CARRY +------------------------------------+ | +-----+ | | | IDC | (NOT CHANGED) | | +-----+ | +---+ | +------------------------------+ | | C | +--> 7 > 6 > 5 > 4 > 3 > 2 > 1 > 0+--+ WC=0 +---+ +------------------------------+ ROTATE REGISTER RIGHT WITHOUT CARRY +----------------------------------------------+ | +-----+ | | +-> IDC | | | | +-----+ | | +---+ +-----+-------+----------------+ | +--> C +-----> 7 > 6 > 5 > 4 > 3 > 2 > 1 > 0+--+ WC=1 +---+ +------------------------------+ ROTATE REGISTER RIGHT WITH CARRY COMPARE (COM) The compare control bit determines the type of comparison that is executed with the Compare instructions. Either logical or arithmetic comparisons may be made. The arithmetic compare assumes that the comparison is between 8-bit, two's complement numbers. The logical compare assumes that the comparison is between 8-bit positive binary numbers. When COM is set to 1, the comparisons will be logical, and when COM is set to 0, the comparisons will be arithmetic. CARRY (C) The Carry bit is set by the execution of any add or subtract instruction that results in a carry or borrow out of the high order bit of the ALU. The carry bit is set to 1 by an add instruction that generates a carry, and a subtract instruction that does @{i}not@{ui} generate a borrow. Inversely, an add that does not generate a carry causes the C bit to be cleared, and a subtract instruction that generates a borrow also clears the carry bit. Even though a borrow is indicated by a zero in the Carry bit, the processor will correctly interpret the zero during subtract with borrow operations as in the following table. Low Order bit Low Order bit Carry bit @{u}Minuend Subtrahend Borrow bit Low Order Bit Result@{uu} 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 0 The carry bit may also be set or cleared by rotate instructions as described earlier under "With/Without Carry". To perform an Add with Carry or a Subtract with Borrow, the WC bit must be set. @endnode @node Orga3 "MEMORY ORGANIZATION" The 2650 has a maximum memory addressing capability of 0-32767 locations. Most direct addressing instructions have thirteen bits allocated for the direct address. Since thirteen bits can only address locations 0-8191, a paging system was implemented to accommodate the entire address range. The memory may be thought of as being divided into four pages of 8192 bytes each. The addresses in each page range as in the following chart: @{u}Start Address End Address@{uu} page 0 %0000000000000000 %0011111111111111 0- 8191 page 1 %0100000000000000 %0111111111111111 8192-16383 page 2 %1000000000000000 %1011111111111111 16384-24575 page 3 %1100000000000000 %1111111111111111 24576-32767 The low order 13 bits in every page range through the same set of numbers. These 13 bits are the same 13 bits addressed by non-branch instructions and are also the same 13 bits which are brought out of the 2650 on the address lines ADR0-ADR12. The high order two bits of the 15-bit address are known as the page bits. The page bits when examined by themselves also represent, in binary, the number of the memory page. Thus, the address %0100000001101101 is known as address location 109 in page 1. The page bits, corresponding to ADR13 and AD14, are brought out of the 2650 on pins 19 and 18. These bits may be used for memory access when more than 8192 bytes of memory are connected. There are no instructions to explicitly set the page bits. They may be set through execution of direct or indirect branch or branch-to-subroutine instructions. It may be seen that these instructions have 15 bits allocated for the address and when such an instruction is executed, the two high order address bits are set into the page bit latches in the 2650 processor and will appear on ADR13 and ADR14 during memory accesses until they are specifically changed. For memory access from non-branch instructions, the 13-bit direct address will address the corresponding location within the current page only. However, the non-branch memory access instruction may access any byte in any page through indirect addressing which provides the full 15- bit address. In the case of non-branch instructions, the page bits are only temporarily changed to correspond to the high order two bits of the 15-bit indirect address used to fetch the argument byte. Immediately after the memory access, ADR13 and ADR14 will revert to their previous value. The consequences of this page address system may be summarized by the following statements. 1. The RESET signal clears both page latches, ie. ADR13 and ADR14 are cleared to zero. 2. All non-branch direct memory access instructions address memory within the current page. 3. All non-branch memory access instructions may access any byte of addressable memory through use of indirect addressing which temporarily changes the page bits for the argument access, but which revert back to their previous state immediately following instruction execution. 4. All direct and indirect addressing branch instructions set the page bits to correspond to the high order two bits of the 15 bit address. 5. Programs may @{i}not@{ui} flow across page boundaries, they must branch to set the page bits. 6. Interrupts always drive the processor to page zero. @endnode @node Feat1 "SUBROUTINE LINKAGE" The on-chip stack, along with the Branch-to-Subroutine and Return instructions, provide the facility to transfer control to a subroutine. The subroutine can return control to the program that branched to it via a Return instruction. The stack is eight levels deep which means that a routine may branch to a subroutine, which may branch to another subroutine, etc., eight times before any Return instructions are executed. When designing a system that utilitizes interrupts, it should be remembered that the processor jams a @{"ZBSR" link ZBSR} into the IAR and then executes it. This will cause an entry to be pushed into the on-chip stack like any other Branch-to-Subroutine instruction and may limit the stack depth available in certain programs. When branching to a subroutine, the following sequence of events occurs: 1. The address in the IAR is used to fetch the Branch-to-Subroutine instruction and is then incremented in the Address Adder so that it points to the instruction following the subroutine branch. 2. The Stack Pointer (SP) is incremented by one so that it points to the next Return Address Stack (RAS) location. 3. The contents of the IAR are stored in the stack at the location designated by the Stack Pointer (SP). 4. The operand address contained in the Branch-to-Subroutine instruction (the address of the first instruction of the subroutine) is inserted into the IAR. When returning from a subroutine, this sequence of events occurs: 1. The address in the IAR is used to fetch the return (@{"RETC" link RETC}, @{"RETE" link RETE}) instruction from memory. 2. When the return instruction is recognized by the processor, the contents of the stack entry pointed to by the Stack Pointer (SP) is placed into the IAR. 3. The Stack Pointer (SP) is decremented by one. 4. Instruction execution continues at the address now in the IAR. @endnode @node Feat2 "CONDITION CODE USAGE" The two-bit register, called the Condition Code (CC), is incorporated in the Program Status Word (PSW). It may be seen in the description of the 2650 instructions that the CC is specifically set by every instruction that causes data to be transferred into a general purpose register and it is also set by compare instructions. The reason for this design feature is that after an instruction executes, the CC contains a modest amount of information about the byte of data that has just been manipulated. For example, a program loads register #1 with a byte of unknown data and the CC setting indicates that the byte is positive, negative or zero. The negative indication implies that bit #7 is set to one. Consequently, a data manipulation operation when followed by a conditional branch is often sufficient to determine desired information without resorting to a specific test, thus saving instructions and memory space. In the following example, the CC is used to test the parity of a byte of data which is stored at symbolic memory location CHAR. EQ EQU 0 ;the equal condition code CHAR DATA 2 ;unknown data byte WC EQU $4 ;the With Carry (WC) bit LT EQU 2 ;CC mask CPSL WC ;clear With Carry (WC) bit LODI,r2 -8 ;set up counter SUBZ r0 ;clear reg #0 LODR,r1 CHAR ;get the character (CC is set) LOOP: BCFR,LT G01 ;if not set, don't count (CC is tested) ADDI,r0 +1 ;count the bit G01: RRL,r1 ;move bits left (CC is set) BIRR,r2 LOOP ;loop till done ;Finished, test if reg #0 has a one in low order ;If bit #0 = 1, odd parity. If bit #0 = 0, then even. TMI,r0 $1 BCTR,EQ ODD EVEN: HALT ODD: HALT @endnode @node Inst1 "ADDRESSING MODES" An addressing mode is a method the processor uses for developing argument addresses for machine instructions. The 2650 processor can develop addresses in eight ways: * Register addressing * Immediate addressing * Relative addressing * Relative, indexed addressing * Absolute addressing * Absolute, indirect addressing * Absolute, indexed addressing * Absolute, indirect, indexed addressing However, of these eight addressing modes, only four of them are basic. The others are variations due to indexing and indirection. The following text describes how effective addresses are developed by the processor. @{b}REGISTER ADDRESSING@{ub} All register-to-register instructions are one byte in length. Instructions utilizing this addressing mode appear in this general format. @{u}oooooorr@{uu} 76543210 o: operation code r: register Since there are only two bits designated to specify a register, register zero always contains one of the operands while the other operand is in one of the three registers in the currently selected bank. Register zero may also be specified as the explicit operand giving instructions such as: EORZ r0. In one byte register addressing instructions which have just one operand, any of the currently selected general purpose registers or register zero may be specified, eg. RRL,r0. @{b}IMMEDIATE ADDRESSING@{ub} All immediate addressing instructions are two bytes in length. The first byte contains the operation code and register designation, while the second byte contains data used as the argument during instruction execution. @{u}oooooorr vvvvvvvv@{uu} 76543210 76543210 Byte 0 Byte 1 o: operation code r: register v: two's complement binary number or 8-bit logic mask The second byte, the data byte, may contain a binary number or a logic mask depending on the particular instruction being executed. Any register may be designated in the first byte. @{b}RELATIVE ADDRESSING@{ub} Relative addressing instructions are all two bytes in length and are memory reference instructions. One argument of the instruction is a register and the other argument is the contents of a memory location. The format of relative addressing instructions is: @{u}oooooorr iaaaaaaa@{uu} 76543210 76543210 Byte 0 Byte 1 o: operation code r: register i: indirect addressing flag a: relative displacement The first byte contains the operation code and register designation, while the second byte contains the relative address. Bits #0-#6, byte #1, contain a 7-bit two's complement binary number which can range from -64 to +63. This number is used by the processor to calculate the effective address. The effective address is calculated by adding the address of the first byte following a relative addressing instruction to the relative displacement in the second byte of the instruction. If bit #7, byte #1, is set to "1", the processor will enter an indirect addressing cycle, where the actual operand address will be accessed from the effective address location. See Indirect Addressing. Two of the branch instructions (@{"ZBSR" link ZBSR}, @{"ZBRR" link ZBRR}) allow addressing relative to page zero, byte #0, of memory. In this case, values up to +63 reference the first 63 bytes of page zero and values up to -64 reference the last 64 bytes of page zero. @{b}ABSOLUTE ADDRESSING FOR NON-BRANCH INSTRUCTIONS@{ub} Absolute addressing instructions are all three bytes in length and are memory reference instructions. One argument of the instruction is a register, designated in bits #1 and #0, byte #0; the other argument is the contents of a memory location. The format of absolute addressing instructions is: @{u}oooooorr iccaaaaa aaaaaaaa@{uu} 76543210 76543210 76543210 Byte 0 Byte 1 Byte 2 o: operation code r: index register or argument register i: indirect addressing flag c: index control bits a: address Bits #4-#0, byte #1, and #7-#0, byte #2, contain the absolute address and can address any byte within the same page that the instruction appears in. The index control bits, bits #6 and #5, byte #1, determine how the effective address will be calculated and possibly which register will be the argument during instruction execution. The index control bits have the following interpretation: Index control @{u}Bit #6 Bit #5 Meaning@{uu} 0 0 Non-indexed address 0 1 Indexed with auto-increment 1 0 Indexed with auto-decrement 1 1 Indexed only When the index control bits are 0 and 0, bits #1 and #0 in byte #0 contain the argument register designation and bits #0 to #4, byte #1, and bits #0 to #7, byte #2, contain the effective address. Indirect addressing may be specified by setting bit #7, byte #1, to a one. When the index control bits are 1 and 1, bits #1 and #0 in byte #0 designate the index register and the argument register implicitly becomes register zero. The effective address is calculated by adding the contents of the index register (8-bit absolute integer) to the address field. If indirect addressing is specified, the indirect address is accessed and then the value in the index register is added to the indirect address. This is commonly called post indexing. When the index control bits are 0 and 1, the address is calculated exactly as when the control bits contain 1 and 1 @{i}except@{ui} a binary 1 is added to the contents of the selected index register @{i}before@{ui} the calculation of the effective address proceeds. Similarly, when the index control bits contain 1 and 0, a binary 1 is subtracted from the contents of the selected index register @{i}before@{ui} the effective address is calculated. @{b}ABSOLUTE ADDRESSING FOR BRANCH INSTRUCTIONS@{ub} The three-byte absolute addressing branch instructions deviate slightly in format from ordinary absolute addressing instructions as shown below: @{u}oooooorr ippaaaaa aaaaaaaa@{uu} 76543210 76543210 76543210 Byte 0 Byte 1 Byte 2 o: operation code r: register or condition code mask i: indirect addressing flag p: page a: address The notable difference is that bits #6 and #5, byte #1, are no longer interpreted as Index Control bits, but instead are interpreted as the high order bits of the address field. This means that there is no indexing allowed on most absolute addressing branch instructions, but indexed branches are possible through use of the @{"BXA" link BXA} and @{"BSXA" link BSXA} instructions. The bits #6 and #5, byte #1, are used to set the current page register, thus enabling programs to directly transfer control to another page. See the @{"Memory Organization" link Orga3}, @{"BXA" link BXA} and @{"BSXA" link BSXA} instructions, and Indirect Addressing. @{b}INDIRECT ADDRESSING@{ub} Indirect addressing means that the argument address of an instruction is not specified by the instruction itself, but rather the argument address will be found in the two bytes pointed to by the address field or relative address field, of absolute or relative addressing instructions. In the case of absolute addressing, the value of the index register is added to the indirect address, @{i}not@{ui} to the value in the address field of the instruction. In both cases, the processor will enter the indirect addressing state when the bit designated "I" is set to one. Entering the indirect addressing sequence adds two cycles (6 clock periods) to the execution time of an instruction. Indirect addresses are 15-bit addresses stored right justified in two contiguous bytes of memory. As such, an indirect address may specify any location in addressable memory (0-32767). The high order bit of the two- byte indirect address is not used by the processor. Only single level indirect addressing is implemented. The following examples demonstrate indirect addressing. %00001110 %10000000 %01010001 LODA,r2 *$51 Address $10 Address $11 Address $12 %00000001 %00101000 ACON $128 Address $51 Address $52 %01100111 DATA $67 Address $128 The LODA instruction in memory locations $10, $11 and $12 specifies indirect addressing (bit #7, byte #1, is set). Therefore, when the instruction is executed, the processor takes the address field value, $51, and uses it to access the two-byte indirect address at $51 and $52. Then using the contents of $51 and $52 as the effective address, the data byte containing $67 is loaded into register #2. %00001010 %10000101 LODR,r2 *$17 Address $10 Address $11 %00000001 %00101000 ACON $128 Address $17 Address $18 %01100111 DATA $67 Address $128 In a fashion similar to the previous example, the relative address is used to access the indirect address which points to the data byte. When the LODR instruction is execute, the data byte contents, $67, will be loaded into register #2. @{b}INSTRUCTION FORMAT EXCEPTIONS@{ub} There are several instructions which are detect by decoding the entire 8 bits of the first byte of the instruction. These instructions are unique and may be noticed in the instruction descriptions. Examples are: @{"HALT" link HALT}, @{"CPSU" link CPSU}, @{"CPSL" link CPSL}. Of this type of instruction, two operation codes were taken from otherwise complete sets thus eliminating certain possible operations. The cases are as follows: (NOT OKAY) STRZ r0 Storing register zero into register zero is not (OKAY) NOP implemented, the operation code is used for NOP (no operation). (NOT OKAY) ANDZ r0 AND of register zero with register zero is not (OKAY) HALT implemented, the operation code is used for HALT. @endnode @node Inst2 "INSTRUCTION FORMATS" (Z) REGISTER ADDRESSING oooooorr o: operation code r: register number/value or condition (I) IMMEDIATE ADDRESSING oooooorr vvvvvvvv o: operation code r: register number v: data mask or binary value (R) RELATIVE ADDRESSING oooooorr iaaaaaaa o: operation code r: register number/value or condition i: indirect bit a: relative displacement (-64 <= displacement <= +63) (A) ABSOLUTE ADDRESSING oooooorr iccaaaaa aaaaaaaa (NON-BRANCH INSTRUCTIONS) o: operation code r: register number/index register number i: indirect bit c: index control bits a: absolute address (B) ABSOLUTE ADDRESSING oooooorr ippaaaaa aaaaaaaa (BRANCH INSTRUCTIONS) o: operation code r: register number/value or condition i: indirect bit p: page a: absolute address INDIRECT ADDRESSING uppaaaaa aaaaaaaa u: unused p: page a: absolute address (E) MISCELLANEOUS oooooooo INSTRUCTIONS o: operation code Index control: %00 = non-indexed %01 = indexed with auto-increment %10 = indexed with auto-decrement %11 = indexed only @endnode @node Alph "ALPHABETIC LISTING" @{" ADDA " link ADDA} @{" ADDI " link ADDI} @{" ADDR " link ADDR} @{" ADDZ " link ADDZ} @{" ANDA " link ANDA} @{" ANDI " link ANDI} @{" ANDR " link ANDR} @{" ANDZ " link ANDZ} @{" BCFA " link BCFA} @{" BCFR " link BCFR} @{" BCTA " link BCTA} @{" BCTR " link BCTR} @{" BDRA " link BDRA} @{" BDRR " link BDRR} @{" BIRA " link BIRA} @{" BIRR " link BIRR} @{" BRNA " link BRNA} @{" BRNR " link BRNR} @{" BSNA " link BSNA} @{" BSNR " link BSNR} @{" BSFA " link BSFA} @{" BSFR " link BSFR} @{" BSTA " link BSTA} @{" BSTR " link BSTR} @{" BSXA " link BSXA} @{" BXA " link BXA } @{" COMA " link COMA} @{" COMI " link COMI} @{" COMR " link COMR} @{" COMZ " link COMZ} @{" CPSL " link CPSL} @{" CPSU " link CPSU} @{" DAR " link DAR } @{" EORA " link EORA} @{" EORI " link EORI} @{" EORR " link EORR} @{" EORZ " link EORZ} @{" HALT " link HALT} @{" IORA " link IORA} @{" IORI " link IORI} @{" IORR " link IORR} @{" IORZ " link IORZ} @{" LODA " link LODA} @{" LODI " link LODI} @{" LODR " link LODR} @{" LODZ " link LODZ} @{" LDPL " link LDPL}* @{" LPSL " link LPSL} @{" LPSU " link LPSU} @{" NOP " link NOP } @{" PPSL " link PPSL} @{" PPSU " link PPSU} @{" REDC " link REDC} @{" REDD " link REDD} @{" REDE " link REDE} @{" RETC " link RETC} @{" RETE " link RETE} @{" RRL " link RRL } @{" RRR " link RRR } @{" SPSL " link SPSL} @{" SPSU " link SPSU} @{" STPL " link STPL}* @{" STRA " link STRA} @{" STRR " link STRR} @{" STRZ " link STRZ} @{" SUBA " link SUBA} @{" SUBI " link SUBI} @{" SUBR " link SUBR} @{" SUBZ " link SUBZ} @{" TMI " link TMI } @{" TPSL " link TPSL} @{" TPSU " link TPSU} @{" WRTC " link WRTC} @{" WRTD " link WRTD} @{" WRTE " link WRTE} @{" ZBRR " link ZBRR} @{" ZBSR " link ZBSR} @endnode @node Nume "NUMERIC LISTING" $00 @{" Indeterminate " link Nume} $80 @{" ADDZ r0 " link ADDZ} $01 @{" LODZ r1 " link LODZ} $81 @{" ADDZ r1 " link ADDZ} $02 @{" LODZ r2 " link LODZ} $82 @{" ADDZ r2 " link ADDZ} $03 @{" LODZ r3 " link LODZ} $83 @{" ADDZ r3 " link ADDZ} $04 @{" LODI,r0 " link LODI} $84 @{" ADDI,r0 " link ADDI} $05 @{" LODI,r1 " link LODI} $85 @{" ADDI,r1 " link ADDI} $06 @{" LODI,r2 " link LODI} $86 @{" ADDI,r2 " link ADDI} $07 @{" LODI,r3 " link LODI} $87 @{" ADDI,r3 " link ADDI} $08 @{" LODR,r0 " link LODR} $88 @{" ADDR,r0 " link ADDR} $09 @{" LODR,r1 " link LODR} $89 @{" ADDR,r1 " link ADDR} $0A @{" LODR,r2 " link LODR} $8A @{" ADDR,r2 " link ADDR} $0B @{" LODR,r3 " link LODR} $8B @{" ADDR,r3 " link ADDR} $0C @{" LODA,r0 " link LODA} $8C @{" ADDA,r0 " link ADDA} $0D @{" LODA,r1 " link LODA} $8D @{" ADDA,r1 " link ADDA} $0E @{" LODA,r2 " link LODA} $8E @{" ADDA,r2 " link ADDA} $0F @{" LODA,r3 " link LODA} $8F @{" ADDA,r3 " link ADDA} $10 @{" LDPL " link LDPL}* $90 @{" Undefined " link Nume} $11 @{" STPL " link STPL}* $91 @{" Undefined " link Nume} $12 @{" SPSU " link SPSU} $92 @{" LPSU " link LPSU} $13 @{" SPSL " link SPSL} $93 @{" LPSL " link LPSL} $14 @{" RETC,eq " link RETC} $94 @{" DAR,r0 " link DAR } $15 @{" RETC,gt " link RETC} $95 @{" DAR,r1 " link DAR } $16 @{" RETC,lt " link RETC} $96 @{" DAR,r2 " link DAR } $17 @{" RETC,un " link RETC} $97 @{" DAR,r3 " link DAR } $18 @{" BCTR,eq " link BCTR} $98 @{" BCFR,eq " link BCFR} $19 @{" BCTR,gt " link BCTR} $99 @{" BCFR,gt " link BCFR} $1A @{" BCTR,lt " link BCTR} $9A @{" BCFR,lt " link BCFR} $1B @{" BCTR,un " link BCTR} $9B @{" ZBRR " link ZBRR} $1C @{" BCTA,eq " link BCTA} $9C @{" BCFA,eq " link BCFA} $1D @{" BCTA,gt " link BCTA} $9D @{" BCFA,gt " link BCFA} $1E @{" BCTA,lt " link BCTA} $9E @{" BCFA,lt " link BCFA} $1F @{" BCTA,un " link BCTA} $9F @{" BXA,r3 " link BXA } $20 @{" EORZ r0 " link EORZ} $A0 @{" SUBZ r0 " link SUBZ} $21 @{" EORZ r1 " link EORZ} $A1 @{" SUBZ r1 " link SUBZ} $22 @{" EORZ r2 " link EORZ} $A2 @{" SUBZ r2 " link SUBZ} $23 @{" EORZ r3 " link EORZ} $A3 @{" SUBZ r3 " link SUBZ} $24 @{" EORI,r0 " link EORI} $A4 @{" SUBI,r0 " link SUBI} $25 @{" EORI,r1 " link EORI} $A5 @{" SUBI,r1 " link SUBI} $26 @{" EORI,r2 " link EORI} $A6 @{" SUBI,r2 " link SUBI} $27 @{" EORI,r3 " link EORI} $A7 @{" SUBI,r3 " link SUBI} $28 @{" EORR,r0 " link EORR} $A8 @{" SUBR,r0 " link SUBR} $29 @{" EORR,r1 " link EORR} $A9 @{" SUBR,r1 " link SUBR} $2A @{" EORR,r2 " link EORR} $AA @{" SUBR,r2 " link SUBR} $2B @{" EORR,r3 " link EORR} $AB @{" SUBR,r3 " link SUBR} $2C @{" EORA,r0 " link EORA} $AC @{" SUBA,r0 " link SUBA} $2D @{" EORA,r1 " link EORA} $AD @{" SUBA,r1 " link SUBA} $2E @{" EORA,r2 " link EORA} $AE @{" SUBA,r2 " link SUBA} $2F @{" EORA,r3 " link EORA} $AF @{" SUBA,r3 " link SUBA} $30 @{" REDC,r0 " link REDC} $B0 @{" WRTC,r0 " link WRTC} $31 @{" REDC,r1 " link REDC} $B1 @{" WRTC,r1 " link WRTC} $32 @{" REDC,r2 " link REDC} $B2 @{" WRTC,r3 " link WRTC} $33 @{" REDC,r3 " link REDC} $B3 @{" WRTC,r3 " link WRTC} $34 @{" RETE,eq " link RETE} $B4 @{" TPSU " link TPSU} $35 @{" RETE,gt " link RETE} $B5 @{" TPSL " link TPSL} $36 @{" RETE,lt " link RETE} $B6 @{" Undefined " link Nume} $37 @{" RETE,un " link RETE} $B7 @{" Undefined " link Nume} $38 @{" BSTR,eq " link BSTR} $B8 @{" BSFR,eq " link BSFR} $39 @{" BSTR,gt " link BSTR} $B9 @{" BSFR,gt " link BSFR} $3A @{" BSTR,lt " link BSTR} $BA @{" BSFR,lt " link BSFR} $3B @{" BSTR,un " link BSTR} $BB @{" ZBSR " link ZBSR} $3C @{" BSTA,eq " link BSTA} $BC @{" BSFA,eq " link BSFA} $3D @{" BSTA,gt " link BSTA} $BD @{" BSFA,gt " link BSFA} $3E @{" BSTA,lt " link BSTA} $BE @{" BSFA,lt " link BSFA} $3F @{" BSTA,un " link BSTA} $BF @{" BSXA,r3 " link BSXA} $40 @{" HALT " link HALT} $C0 @{" NOP " link NOP } $41 @{" ANDZ r1 " link ANDZ} $C1 @{" STRZ r1 " link STRZ} $42 @{" ANDZ r2 " link ANDZ} $C2 @{" STRZ r2 " link STRZ} $43 @{" ANDZ r3 " link ANDZ} $C3 @{" STRZ r3 " link STRZ} $44 @{" ANDI,r0 " link ANDI} $C4 @{" Undefined " link Nume} $45 @{" ANDI,r1 " link ANDI} $C5 @{" Undefined " link Nume} $46 @{" ANDI,r2 " link ANDI} $C6 @{" Undefined " link Nume} $47 @{" ANDI,r3 " link ANDI} $C7 @{" Undefined " link Nume} $48 @{" ANDR,r0 " link ANDR} $C8 @{" STRR,r0 " link STRR} $49 @{" ANDR,r1 " link ANDR} $C9 @{" STRR,r1 " link STRR} $4A @{" ANDR,r2 " link ANDR} $CA @{" STRR,r2 " link STRR} $4B @{" ANDR,r3 " link ANDR} $CB @{" STRR,r3 " link STRR} $4C @{" ANDA,r0 " link ANDA} $CC @{" STRA,r0 " link STRA} $4D @{" ANDA,r1 " link ANDA} $CD @{" STRA,r1 " link STRA} $4E @{" ANDA,r2 " link ANDA} $CE @{" STRA,r2 " link STRA} $4F @{" ANDA,r3 " link ANDA} $CF @{" STRA,r3 " link STRA} $50 @{" RRR,r0 " link RRR } $D0 @{" RRL,r0 " link RRL } $51 @{" RRR,r1 " link RRR } $D1 @{" RRL,r1 " link RRL } $52 @{" RRR,r2 " link RRR } $D2 @{" RRL,r2 " link RRL } $53 @{" RRR,r3 " link RRR } $D3 @{" RRL,r3 " link RRL } $54 @{" REDE,r0 " link REDE} $D4 @{" WRTE,r0 " link WRTE} $55 @{" REDE,r1 " link REDE} $D5 @{" WRTE,r1 " link WRTE} $56 @{" REDE,r2 " link REDE} $D6 @{" WRTE,r2 " link WRTE} $57 @{" REDE,r3 " link REDE} $D7 @{" WRTE,r3 " link WRTE} $58 @{" BRNR,r0 " link BRNR} $D8 @{" BIRR,r0 " link BIRR} $59 @{" BRNR,r1 " link BRNR} $D9 @{" BIRR,r1 " link BIRR} $5A @{" BRNR,r2 " link BRNR} $DA @{" BIRR,r2 " link BIRR} $5B @{" BRNR,r3 " link BRNR} $DB @{" BIRR,r3 " link BIRR} $5C @{" BRNA,r0 " link BRNA} $DC @{" BIRA,r0 " link BIRA} $5D @{" BRNA,r1 " link BRNA} $DD @{" BIRA,r1 " link BIRA} $5E @{" BRNA,r2 " link BRNA} $DE @{" BIRA,r2 " link BIRA} $5F @{" BRNA,r3 " link BRNA} $DF @{" BIRA,r3 " link BIRA} $60 @{" IORZ r0 " link IORZ} $E0 @{" COMZ,r0 " link COMZ} $61 @{" IORZ r1 " link IORZ} $E1 @{" COMZ,r1 " link COMZ} $62 @{" IORZ r2 " link IORZ} $E2 @{" COMZ,r2 " link COMZ} $63 @{" IORZ r3 " link IORZ} $E3 @{" COMZ,r3 " link COMZ} $64 @{" IORI,r0 " link IORI} $E4 @{" COMI,r0 " link COMI} $65 @{" IORI,r1 " link IORI} $E5 @{" COMI,r1 " link COMI} $66 @{" IORI,r2 " link IORI} $E6 @{" COMI,r2 " link COMI} $67 @{" IORI,r3 " link IORI} $E7 @{" COMI,r3 " link COMI} $68 @{" IORR,r0 " link IORR} $E8 @{" COMR,r0 " link COMR} $69 @{" IORR,r1 " link IORR} $E9 @{" COMR,r1 " link COMR} $6A @{" IORR,r2 " link IORR} $EA @{" COMR,r2 " link COMR} $6B @{" IORR,r3 " link IORR} $EB @{" COMR,r3 " link COMR} $6C @{" IORA,r0 " link IORA} $EC @{" COMA,r0 " link COMA} $6D @{" IORA,r1 " link IORA} $ED @{" COMA,r1 " link COMA} $6E @{" IORA,r2 " link IORA} $EE @{" COMA,r2 " link COMA} $6F @{" IORA,r3 " link IORA} $EF @{" COMA,r3 " link COMA} $70 @{" REDD,r0 " link REDD} $F0 @{" WRTD,r0 " link WRTD} $71 @{" REDD,r1 " link REDD} $F1 @{" WRTD,r1 " link WRTD} $72 @{" REDD,r2 " link REDD} $F2 @{" WRTD,r2 " link WRTD} $73 @{" REDD,r3 " link REDD} $F3 @{" WRTD,r3 " link WRTD} $74 @{" CPSU " link CPSU} $F4 @{" TMI,r0 " link TMI } $75 @{" CPSL " link CPSL} $F5 @{" TMI,r1 " link TMI } $76 @{" PPSU " link PPSU} $F6 @{" TMI,r2 " link TMI } $77 @{" PPSL " link PPSL} $F7 @{" TMI,r3 " link TMI } $78 @{" BSNR,r0 " link BSNR} $F8 @{" BDRR,r0 " link BDRR} $79 @{" BSNR,r1 " link BSNR} $F9 @{" BDRR,r1 " link BDRR} $7A @{" BSNR,r2 " link BSNR} $FA @{" BDRR,r2 " link BDRR} $7B @{" BSNR,r3 " link BSNR} $FB @{" BDRR,r3 " link BDRR} $7C @{" BSNA,r0 " link BSNA} $FC @{" BDRA,r0 " link BDRA} $7D @{" BSNA,r1 " link BSNA} $FD @{" BDRA,r1 " link BDRA} $7E @{" BSNA,r2 " link BSNA} $FE @{" BDRA,r2 " link BDRA} $7F @{" BSNA,r3 " link BSNA} $FF @{" BDRA,r3 " link BDRA} * = 2650-B only @endnode @node Func "ORGANIZED BY FUNCTION" LOAD/STORE @{"LODZ" link LODZ} @{"LODI" link LODI} @{"LODR" link LODR} @{"LODA" link LODA} @{"STRZ" link STRZ} @{"STRR" link STRR} @{"STRA" link STRA} ARITHMETIC @{"ADDZ" link ADDZ} @{"ADDI" link ADDI} @{"ADDR" link ADDR} @{"ADDA" link ADDA} @{"SUBZ" link SUBZ} @{"SUBI" link SUBI} @{"SUBR" link SUBR} @{"SUBA" link SUBA} LOGICAL @{"IORZ" link IORZ} @{"IORI" link IORI} @{"IORR" link IORR} @{"IORA" link IORA} @{"EORZ" link EORZ} @{"EORI" link EORI} @{"EORR" link EORR} @{"EORA" link EORA} @{"ANDZ" link ANDZ} @{"ANDI" link ANDI} @{"ANDR" link ANDR} @{"ANDA" link ANDA} BRANCH @{"BCTR" link BCTR} @{"BCTA" link BCTA} @{"BCFR" link BCFR} @{"BCFA" link BCFA} @{"BRNR" link BRNR} @{"BRNA" link BRNA} @{"BIRR" link BIRR} @{"BIRA" link BIRA} @{"BDRR" link BDRR} @{"BDRA" link BDRA} @{"BXA " link BXA } @{"ZBRR" link ZBRR} SUBROUTINE BRANCH @{"BSTR" link BSTR} @{"BSTA" link BSTA} @{"BSFR" link BSFR} @{"BSFA" link BSFA} @{"BSNR" link BSNR} @{"BSNA" link BSNA} @{"BSXA" link BSXA} @{"ZBSR" link ZBSR} SUBROUTINE RETURN @{"RETC" link RETC} @{"RETE" link RETE} COMPARISON @{"COMZ" link COMZ} @{"COMI" link COMI} @{"COMR" link COMR} @{"COMA" link COMA} INPUT/OUTPUT @{"REDC" link REDC} @{"REDD" link REDD} @{"WRTC" link WRTC} @{"WRTD" link WRTD} @{"REDE" link REDE} @{"WRTE" link WRTE} PROGRAM STATUS MANIPULATION @{"LDPL" link LDPL}* @{"LPSU" link LPSU} @{"LPSL" link LPSL} @{"SPSU" link SPSU} @{"SPSL" link SPSL} @{"STPL" link STPL}* @{"CPSU" link CPSU} @{"CPSL" link CPSL} @{"PPSU" link PPSU} @{"PPSL" link PPSL} @{"TPSU" link TPSU} @{"TPSL" link TPSL} ROTATE @{"RRR " link RRR } @{"RRL " link RRL } MISCELLANEOUS @{"NOP " link NOP } @{"HALT" link HALT} @{"TMI " link TMI } @{"DAR " link DAR } * = 2650-B only @endnode @node ADDA "ADDA" @{b}ADD ABSOLUTE@{ub} @{b}Addressing Mode:@{ub} Absolute @{b}Size:@{ub} 3 bytes @{b}Signetics Mnemonic:@{ub} ADDA,r (*)a(,X) @{b}CALM Mnemonic:@{ub} ADD r,m ADD r,\@m ADD A,(r)+m ADD A,(r)+\@m ADD A,(+r)+m ADD A,(+r)+\@m ADD A,(-r)+m ADD A,(-r)+\@m ADDC r,m ADDC r,\@m ADDC A,(r)+m ADDC A,(r)+\@m ADDC A,(+r)+m ADDC A,(+r)+\@m ADDC A,(-r)+m ADDC A,(-r)+\@m @{b}Binary Code:@{ub} $8C-$8F @{u}100011rr iccaaaaa aaaaaaaa@{uu} 76543210 76543210 76543210 r: register (2 bits) i: indirect addressing flag (1 bit) c: index control bits (2 bits) a: absolute address (13 bits) @{b}Execution Time:@{ub} 4 cycles (12 clock periods) @{b}Processor Registers Affected:@{ub} C, CC, IDC, OVF @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This three-byte instruction causes the contents of register r and the contents of the byte of memory pointed to by the effective address to be added together in a true binary adder. The eight-bit sum replaces the contents of register r. Indirect addressing and/or indexing may be specified. If indexing is specified, bits #1 and #0, byte #0, indicate the index register and the destination of the operation implicitly becomes register zero. @{b}Note:@{ub} Add with Carry may be effected. See Carry (C) bit. @{b}Pseudocode:@{ub} ADDA,rn $aaaa ;rn += *($aaaa); ;4,3 ADDA,r0 $aaaa,rn ;r0 += *($aaaa + rn); ;4,3 ADDA,r0 $aaaa,rn+ ;r0 += *($aaaa + ++rn); ;4,3 ;or, rn++; r0 += *($aaaa + rn); ADDA,r0 $aaaa,rn- ;r0 += *($aaaa + --rn); ;4,3 ;or, rn--; r0 += *($aaaa + rn); ADDA,rn *$aaaa ;rn += *(*($aaaa)); ;6,3 ADDA,r0 *$aaaa,rn ;r0 += *(*($aaaa) + rn); ;6,3 ADDA,r0 *$aaaa,rn+ ;r0 += *(*($aaaa) + ++rn); ;6,3 ;or, rn++; r0 += *(*($aaaa) + rn); ADDA,r0 *$aaaa,rn- ;r0 += *(*($aaaa) + --rn); ;6,3 ;or, rn--; r0 += *(*($aaaa) + rn); @endnode @node ADDI "ADDI" @{b}ADD IMMEDIATE@{ub} @{b}Addressing Mode:@{ub} Immediate @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} ADDI,r v @{b}CALM Mnemonic:@{ub} ADD r,#v ADDC r,#v @{b}Binary Code:@{ub} $84-$87 @{u}100001rr vvvvvvvv@{uu} 76543210 76543210 r: register (2 bits) v: value (8 bits) @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} C, CC, IDC, OVF @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This two-byte instruction causes the contents of register r and the contents of the second byte of this instruction to be added together in a true binary adder. The eight-bit sum replaces the contents of register r. @{b}Note:@{ub} Add with Carry may be effected. See Carry (C) bit. @{b}Pseudocode:@{ub} ADDI,rn $vv ;rn += $vv; ;2,2 @endnode @node ADDR "ADDR" @{b}ADD RELATIVE@{ub} @{b}Addressing Mode:@{ub} Relative @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} ADDR,r (*)a @{b}CALM Mnemonic:@{ub} ADD r,·+®' ADD r,\@·+®' ADDC r,·+®' ADDC r,\@·+®' @{b}Binary Code:@{ub} $88-$8B @{u}100010rr iaaaaaaa@{uu} 76543210 76543210 r: register (2 bits) i: indirect addressing flag (1 bit) a: relative address (7 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} C, CC, IDC, OVF @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This two-byte instruction causes the contents of register r and the contents of the byte of memory pointed to by the effective address to be added together in a true binary adder. The eight-bit sum replaces the contents of register r. Indirect addressing may be specified. @{b}Note:@{ub} Add with Carry may be effected. See Carry (C) bit. @{b}Pseudocode:@{ub} ADDR,rn $aaaa ;rn += *($aaaa); ;3,2 ADDR,rn *$aaaa ;rn += *(*($aaaa)); ;5,2 @endnode @node ADDZ "ADDZ" @{b}ADD TO REGISTER ZERO@{ub} @{b}Addressing Mode:@{ub} Register @{b}Size:@{ub} 1 byte @{b}Signetics Mnemonic:@{ub} ADDZ r @{b}CALM Mnemonic:@{ub} ADD A,r ADDC A,r @{b}Binary Code:@{ub} $80-$83 @{u}100000rr@{uu} 76543210 r: register (2 bits) @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} C, CC, IDC, OVF @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This one-byte instruction causes the contents of the specified register, r, and the contents of register zero to be added together in a true binary adder. The eight-bit sum of the addition replaces the contents of register zero. The contents of register r remain unchanged. @{b}Note:@{ub} Add with Carry may be effected. See Carry (C) bit. @{b}Pseudocode:@{ub} ADDZ rn ;r0 += rn; ;2,1 @endnode @node ANDA "ANDA" @{b}AND ABSOLUTE@{ub} @{b}Addressing Mode:@{ub} Absolute @{b}Size:@{ub} 3 bytes @{b}Signetics Mnemonic:@{ub} ANDA,r (*)a(,X) @{b}CALM Mnemonic:@{ub} AND r,m AND r,\@m AND A,(r)+m AND A,(r)+\@m AND A,(+r)+m AND A,(+r)+\@m AND A,(-r)+m AND A,(-r)+\@m @{b}Binary Code:@{ub} $4C-$4F @{u}010011rr iccaaaaa aaaaaaaa@{uu} 76543210 76543210 76543210 r: register (2 bits) i: indirect addressing flag (1 bit) c: index control bits (2 bits) a: absolute address (13 bits) @{b}Execution Time:@{ub} 4 cycles (12 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This three-byte instruction causes the contents of register r to be logically ANDed with the contents of the memory byte pointed to by the effective address. The result of the operation replaces the contents of register r. The AND operation treats each bit of the argument bytes as in the truth table below: @{u}Bit (0-7) Bit (0-7) AND Result@{uu} 0 0 0 0 1 0 1 1 1 1 0 0 Indirect addressing and/or indexing may be specified. If indexing is specified, bits #1 and #0, byte #0, indicate the index register and the destination of the operation implicitly becomes register zero. @{b}Pseudocode:@{ub} ANDA,rn $aaaa ;r0 &= *($aaaa); ;4,3 ANDA,r0 $aaaa,rn ;r0 &= *($aaaa + rn); ;4,3 ANDA,r0 $aaaa,rn+ ;r0 &= *($aaaa + ++rn); ;4,3 ;or, rn++; r0 &= *($aaaa + rn); ANDA,r0 $aaaa,rn- ;r0 &= *($aaaa + --rn); ;4,3 ;or, rn--; r0 &= *($aaaa + rn); ANDA,rn *$aaaa ;rn &= *(*($aaaa)); ;6,3 ANDA,r0 *$aaaa,rn ;r0 &= *(*($aaaa) + rn); ;6,3 ANDA,r0 *$aaaa,rn+ ;r0 &= *(*($aaaa) + ++rn); ;6,3 ;or, rn++; r0 &= *(*($aaaa) + rn); ANDA,r0 *$aaaa,rn- ;r0 &= *(*($aaaa) + --rn); ;6,3 ;or, rn--; r0 &= *(*($aaaa) + rn); @endnode @node ANDI "ANDI" @{b}AND IMMEDIATE@{ub} @{b}Addressing Mode:@{ub} Immediate @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} ANDI,r v @{b}CALM Mnemonic:@{ub} AND r,#n @{b}Binary Code:@{ub} $44-$47 @{u}010001rr vvvvvvvv@{uu} 76543210 76543210 r: register (2 bits) v: value (8 bits) @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This two-byte instruction causes the contents of register r to be logically ANDed with the contents of the second byte of this instruction. The result of this operation replaces the contents of register r. The AND operation treats each bit of the argument bytes as in the truth table below: @{u}Bit (0-7) Bit (0-7) AND Result@{uu} 0 0 0 0 1 0 1 1 1 1 0 0 @{b}Pseudocode:@{ub} ANDI,rn $vv ;rn &= $vv; ;2,2 @endnode @node ANDR "ANDR" @{b}AND RELATIVE@{ub} @{b}Addressing Mode:@{ub} Relative @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} ANDR,r (*)a @{b}CALM Mnemonic:@{ub} AND r,·+®' AND r,\@·+®' @{b}Binary Code:@{ub} $48-$4B @{u}010010rr iaaaaaaa@{uu} 76543210 76543210 r: register (2 bits) i: indirect addressing flag (1 bit) a: relative address (7 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This two-byte instruction causes the contents of register r to be logically ANDed with the contents of the memory byte pointed to by the effective address. The result of this operation replaces the contents of register r. Indirect indexing may be specified. The AND operation treats each bit of the argument bytes as in the truth table below: @{u}Bit (0-7) Bit (0-7) AND Result@{uu} 0 0 0 0 1 0 1 1 1 1 0 0 @{b}Pseudocode:@{ub} ANDR,rn $aaaa ;rn &= *($aaaa); ;3,2 ANDR,rn *$aaaa ;rn &= *(*($aaaa)); ;5,2 @endnode @node ANDZ "ANDZ" @{b}AND TO REGISTER ZERO@{ub} @{b}Addressing Mode:@{ub} Register @{b}Size:@{ub} 1 byte @{b}Signetics Mnemonic:@{ub} ANDZ r @{b}CALM Mnemonic:@{ub} AND A,r @{b}Binary Code:@{ub} $41-$43 @{u}010000rr@{uu} 76543210 r: register (2 bits) @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This one-byte instruction causes the contents of the specified register, r, to be logically ANDED with the contents of register zero. The result of the operation replaces the contents of register zero. The contents of register r remain unchanged. The AND operation treats each bit of the argument bytes as in the truth table below: @{u}Bit (0-7) Bit (0-7) AND Result@{uu} 0 0 0 0 1 0 1 1 1 1 0 0 @{b}Note:@{ub} Register r may not be specified as zero. This operation code, %01000000, is reserved for HALT. @{b}Pseudocode:@{ub} ANDZ rn ;r0 &= rn; ;2,1 @endnode @node BCFA "BCFA" @{b}BRANCH ON CONDITION FALSE, ABSOLUTE@{ub} @{b}Addressing Mode:@{ub} Absolute @{b}Size:@{ub} 3 bytes @{b}Signetics Mnemonic:@{ub} BCFA,v (*)a @{b}CALM Mnemonic:@{ub} JUMP NE m JUMP NE \@m JUMP LE m JUMP LE \@m JUMP GE m JUMP GE \@m @{b}Binary Code:@{ub} $9C-$9E @{u}100111vv ippaaaaa aaaaaaaa@{uu} 76543210 76543210 76543210 v: condition (2 bits) i: indirect addressing flag (1 bit) p: page (2 bits) a: absolute address (13 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} None @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This three-byte conditional branch instruction causes the processor to fetch the next instruction to be executed from the memory location pointed to by the effective address only if the two-bit v field does not match the current Condition Code (CC) field in the Program Status Word. If there is no match, the contents of the Instruction Address Register (IAR) are replaced by the effective address. If the v field and CC field match, the next instruction is fetched from the location following the third byte of this instruction. Indirect addressing may be specified. The v field may not be set to $3 as this bit combination (%10011111) is used for the @{"BXA" link BXA} operation code. @{b}Pseudocode:@{ub} BCFA,eq $aaaa ;if != goto $aaaa; ;3,3 BCFA,gt $aaaa ;if <= goto $aaaa; ;3,3 BCFA,lt $aaaa ;if >= goto $aaaa; ;3,3 BCFA,eq *$aaaa ;if != goto *($aaaa); ;3+2,3 BCFA,gt *$aaaa ;if <= goto *($aaaa); ;3+2,3 BCFA,lt *$aaaa ;if >= goto *($aaaa); ;3+2,3 @endnode @node BCFR "BCFR" @{b}BRANCH ON CONDITION FALSE, RELATIVE@{ub} @{b}Addressing Mode:@{ub} Relative @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} BCFR,v (*)a @{b}CALM Mnemonic:@{ub} JUMP NE ·+®' JUMP NE \@·+®' JUMP LE ·+®' JUMP LE \@·+®' JUMP GE ·+®' JUMP GE \@·+®' @{b}Binary Code:@{ub} $98-$9A @{u}100110vv iaaaaaaa@{uu} 76543210 76543210 v: condition (2 bits) i: indirect addressing flag (1 bit) a: relative address (7 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} None @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This two-byte conditional branch instruction causes the processor to fetch the next instruction to be executed from the memory location pointed to by the effective address only if the two-bit v field does not match the current Condition Code (CC) field in the Program Status Word. If there is no match, the contents of the Instruction Address Register (IAR) are replaced by the effective address. If the v field and CC field match, the next instruction is fetched from the location following the second byte of this instruction. Indirect addressing may be specified. The v field may not be set to $3 as this bit combination (%10011011) is used for the @{"ZBRR" link ZBRR} operation code. @{b}Pseudocode:@{ub} BCFR,eq $aaaa ;if != goto $aaaa; ;3,2 BCFR,gt $aaaa ;if <= goto $aaaa; ;3,2 BCFR,lt $aaaa ;if >= goto $aaaa; ;3,2 BCFR,eq *$aaaa ;if != goto *($aaaa); ;3+2,2 BCFR,gt *$aaaa ;if <= goto *($aaaa); ;3+2,2 BCFR,lt *$aaaa ;if >= goto *($aaaa); ;3+2,2 @endnode @node BCTA "BCTA" @{b}BRANCH ON CONDITION TRUE, ABSOLUTE@{ub} @{b}Addressing Mode:@{ub} Absolute @{b}Size:@{ub} 3 bytes @{b}Signetics Mnemonic:@{ub} BCTA,v (*)a @{b}CALM Mnemonic:@{ub} JUMP EQ m or JUMP AO m JUMP EQ \@m or JUMP AO \@m JUMP GT m JUMP GT \@m JUMP LT m or JUMP NO m JUMP LT \@m or JUMP NO \@m JUMP m JUMP \@m @{b}Binary Code:@{ub} $1C-$1F @{u}000111vv ippaaaaa aaaaaaaa@{uu} 76543210 76543210 76543210 v: condition (2 bits) i: indirect addressing flag (1 bit) p: page (2 bits) a: absolute address (13 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} None @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This three-byte conditional branch instruction causes the processor to fetch the next instruction to be executed from the memory location pointed to by the effective address only if the two-bit v field matches the current Condition Code (CC) field in the Program Status Word. If there is a match, the contents of the Instruction Address Register (IAR) are replaced by the effective address. If the v field and CC field do not match, the next instruction is fetched from the location following the third byte of this instruction. Indirect addressing may be specified. If the v field is set to $3, an unconditional branch is effected. @{b}Pseudocode:@{ub} BCTA,eq $aaaa ;if == goto $aaaa; ;3,3 BCTA,gt $aaaa ;if > goto $aaaa; ;3,3 BCTA,lt $aaaa ;if < goto $aaaa; ;3,3 BCTA,un $aaaa ;goto $aaaa; ;3,3 BCTA,eq *$aaaa ;if == goto *($aaaa); ;3+2,3 BCTA,gt *$aaaa ;if > goto *($aaaa); ;3+2,3 BCTA,lt *$aaaa ;if < goto *($aaaa); ;3+2,3 BCTA,un *$aaaa ;goto *($aaaa); ;5,3 @endnode @node BCTR "BCTR" @{b}BRANCH ON CONDITION TRUE, RELATIVE@{ub} @{b}Addressing Mode:@{ub} Relative @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} BCTR,v (*)a @{b}CALM Mnemonic:@{ub} JUMP EQ ·+®' or JUMP AO ·+®' JUMP EQ \@·+®' or JUMP AO \@·+®' JUMP GT ·+®' JUMP GT \@·+®' JUMP LT ·+®' or JUMP NO ·+®' JUMP LT \@·+®' or JUMP NO \@·+®' JUMP ·+®' JUMP \@·+®' @{b}Binary Code:@{ub} $18-$1B @{u}000110vv iaaaaaaa@{uu} 76543210 76543210 v: condition (2 bits) i: indirect addressing flag (1 bit) a: relative address (7 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} None @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This two-byte conditional branch instruction causes the processor to fetch the next instruction to be executed from the memory location pointed to by the effective address only if the two-bit v field matches the current Condition Code (CC) field in the Program Status Word. If there is a match, the contents of the Instruction Address Register (IAR) are replaced by the effective address. If the v field and CC field do not match, the next instruction is fetched from the location following the second byte of this instruction. Indirect addressing may be specified. If the v field is set to $3, an unconditional branch is effected. @{b}Pseudocode:@{ub} BCTR,eq $aaaa ;if == goto $aaaa; ;3,2 BCTR,gt $aaaa ;if > goto $aaaa; ;3,2 BCTR,lt $aaaa ;if < goto $aaaa; ;3,2 BCTR,un $aaaa ;goto $aaaa; ;3,2 BCTR,eq *$aaaa ;if == goto *($aaaa); ;3+2,2 BCTR,gt *$aaaa ;if > goto *($aaaa); ;3+2,2 BCTR,lt *$aaaa ;if < goto *($aaaa); ;3+2,2 BCTR,un *$aaaa ;goto *($aaaa); ;5,2 @endnode @node BDRA "BDRA" @{b}BRANCH ON DECREMENTING REGISTER, ABSOLUTE@{ub} @{b}Addressing Mode:@{ub} Absolute @{b}Size:@{ub} 3 bytes @{b}Signetics Mnemonic:@{ub} BDRA,r (*)a @{b}CALM Mnemonic:@{ub} DECJ,NE r,m DECJ,NE r,\@m @{b}Binary Code:@{ub} $FC-$FF @{u}111111rr ippaaaaa aaaaaaaa@{uu} 76543210 76543210 76543210 r: register (2 bits) i: indirect addressing flag (1 bit) p: page (2 bits) a: absolute address (13 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} None @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This three-byte branch instruction causes the processor to decrement the contents of the specified register by one. If the new value in the register is non-zero, the next instruction to be executed is taken from the memory location pointed to by the effective address, ie. the effective address replaces the previous contents of the Instruction Address Register (IAR). If the new value in register r is zero, the next instruction to be executed follows the second byte of this instruction. Indirect addressing may be specified. @{b}Pseudocode:@{ub} BDRA,rn $aaaa ;if (--rn != 0) goto $aaaa; ;3,3 ;or, rn--; if (rn != 0) goto $aaaa; BDRA,rn *$aaaa ;if (--rn != 0) goto *($aaaa); ;3+2,3 ;or, rn--; if (rn != 0) goto *($aaaa); @endnode @node BDRR "BDRR" @{b}BRANCH ON DECREMENTING REGISTER, RELATIVE@{ub} @{b}Addressing Mode:@{ub} Relative @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} BDRR,r (*)a @{b}CALM Mnemonic:@{ub} DECJ,NE r,·+®' DECJ,NE r,\@·+®' @{b}Binary Code:@{ub} $F8-$FB @{u}111110rr iaaaaaaa@{uu} 76543210 76543210 r: register (2 bits) i: indirect addressing flag (1 bit) a: relative address (7 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} None @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This two-byte branch instruction causes the processor to decrement the contents of the specified register by one. If the new value in the register is non-zero, the next instruction to be executed is taken from the memory location pointed to by the effective address, ie. the effective address replaces the previous contents of the Instruction Address Register (IAR). If the new value in register r is zero, the next instruction to be executed follows the second byte of this instruction. Indirect addressing may be specified. @{b}Pseudocode:@{ub} BDRR,rn $aaaa ;if (--rn != 0) goto $aaaa; ;3,2 ;or, rn--; if (rn != 0) goto $aaaa; BDRR,rn *$aaaa ;if (--rn != 0) goto *($aaaa); ;3+2,2 ;or, rn--; if (rn != 0) goto *($aaaa); @endnode @node BIRA "BIRA" @{b}BRANCH ON INCREMENTING REGISTER, ABSOLUTE@{ub} @{b}Addressing Mode:@{ub} Absolute @{b}Size:@{ub} 3 bytes @{b}Signetics Mnemonic:@{ub} BIRA,r (*)a @{b}CALM Mnemonic:@{ub} INCJ,NE r,m INCJ,NE r,\@m @{b}Binary Code:@{ub} $DC-$DF @{u}110111rr ippaaaaa aaaaaaaa@{uu} 76543210 76543210 76543210 r: register (2 bits) i: indirect addressing flag (1 bit) p: page (2 bits) a: absolute address (13 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} None @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This three-byte branch instruction causes the processor to increment the contents of the specified register by one. If the new value in the register is non-zero, the next instruction to be executed is taken from the memory location pointed to by the effective address, ie. the effective address replaces the previous contents of the Instruction Address Register (IAR). If the new value in register r is zero, the next instruction to be executed follows the second byte of this instruction. Indirect addressing may be specified. @{b}Pseudocode:@{ub} BIRA,rn $aaaa ;if (++rn != 0) goto $aaaa; ;3,3 ;or, rn++; if (rn != 0) goto $aaaa; BIRA,rn *$aaaa ;if (++rn != 0) goto *($aaaa); ;3+2,3 ;or, rn++; if (rn != 0) goto *($aaaa); @endnode @node BIRR "BIRR" @{b}BRANCH ON INCREMENTING REGISTER, RELATIVE@{ub} @{b}Addressing Mode:@{ub} Relative @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} BIRR,r (*)a @{b}CALM Mnemonic:@{ub} INCJ,NE r,·+®' INCJ,NE r,\@·+®' @{b}Binary Code:@{ub} $D8-$DB @{u}110110rr iaaaaaaa@{uu} 76543210 76543210 r: register (2 bits) i: indirect addressing flag (1 bit) a: relative address (7 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} None @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This two-byte branch instruction causes the processor to increment the contents of the specified register by one. If the new value in the register is non-zero, the next instruction to be executed is taken from the memory location pointed to by the effective address, ie. the effective address replaces the previous contents of the Instruction Address Register (IAR). If the new value in register r is zero, the next instruction to be executed follows the second byte of this instruction. Indirect addressing may be specified. @{b}Pseudocode:@{ub} BIRR,rn $aaaa ;if (++rn != 0) goto $aaaa; ;3,2 ;or, rn++; if (rn != 0) goto $aaaa; BIRR,rn *$aaaa ;if (++rn != 0) goto *($aaaa); ;3+2,2 ;or, rn++; if (rn != 0) goto *($aaaa); @endnode @node BRNA "BRNA" @{b}BRANCH ON REGISTER NON-ZERO, ABSOLUTE@{ub} @{b}Addressing Mode:@{ub} Absolute @{b}Size:@{ub} 3 bytes @{b}Signetics Mnemonic:@{ub} BRNA,r (*)a @{b}CALM Mnemonic:@{ub} JUMP rNE m JUMP rNE \@m @{b}Binary Code:@{ub} $5C-$5F @{u}010111rr ippaaaaa aaaaaaaa@{uu} 76543210 76543210 76543210 r: register (2 bits) i: indirect addressing flag (1 bit) p: page (2 bits) a: absolute address (13 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} None @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This three-byte branch instruction causes the contents of the specified register r to be tested for a non-zero value. If the register contains a non-zero value, the next instruction to be executed is taken from the location pointed to by the effective address, ie. the effective address replaces the contents of the Instruction Address Register (IAR). If the specified register contains a zero value the next instruction is fetched from the location following the third byte of this instruction. Indirect addressing may be specified. @{b}Pseudocode:@{ub} BRNA,rn $aaaa ;if (rn != 0) goto $aaaa; ;3,3 BRNA,rn *$aaaa ;if (rn != 0) goto *($aaaa); ;3+2,3 @endnode @node BRNR "BRNR" @{b}BRANCH ON REGISTER NON-ZERO, RELATIVE@{ub} @{b}Addressing Mode:@{ub} Relative @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} BRNR,r (*)a @{b}CALM Mnemonic:@{ub} JUMP rNE ·+®' JUMP rNE \@·+®' @{b}Binary Code:@{ub} $58-$5B @{u}010110rr iaaaaaaa@{uu} 76543210 76543210 r: register (2 bits) i: indirect addressing flag (1 bit) a: relative address (7 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} None @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This two-byte branch instruction causes the contents of the specified register r to be tested for a non-zero value. If the register contains a non-zero value, the next instruction to be executed is taken from the location pointed to by the effective address, ie. the effective address replaces the contents of the Instruction Address Register (IAR). If the specified register contains a zero value the next instruction is fetched from the location following the second byte of this instruction. Indirect addressing may be specified. @{b}Pseudocode:@{ub} BRNR,rn $aaaa ;if (rn != 0) goto $aaaa; ;3,2 BRNR,rn *$aaaa ;if (rn != 0) goto *($aaaa); ;3+2,2 @endnode @node BSFA "BSFA" @{b}BRANCH TO SUBROUTINE ON CONDITION FALSE, ABSOLUTE@{ub} @{b}Addressing Mode:@{ub} Absolute @{b}Size:@{ub} 3 bytes @{b}Signetics Mnemonic:@{ub} BSFA,v (*)a @{b}CALM Mnemonic:@{ub} CALL NE m CALL NE \@m CALL LE m CALL LE \@m CALL GE m CALL GE \@m @{b}Binary Code:@{ub} $BC-$BE @{u}101111vv ippaaaaa aaaaaaaa@{uu} 76543210 76543210 76543210 v: condition (2 bits) i: indirect addressing flag (1 bit) p: page (2 bits) a: absolute address (13 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} SP @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This three-byte conditional subroutine branch instruction causes the processor to perform a subroutine branch only if the two-bit v field does not match the current Condition Code (CC) field in the Program Status Word (PSW). If the fields do not match, the Stack Pointer (SP) is incremented by one and the current contents of the Instruction Address Register (IAR), which points to the location following the third byte of this instruction, is pushed into the Return Address Stack (RAS). The effective address replaces the previous contents of the IAR. If the v field and CC field match, the next instruction is fetched from the location following the third byte of this instruction and the Stack Pointer (SP) is unaffected. Indirect addressing may be specified. If the v field may not be coded as $3 as this bit combination (%10111111) is used for the @{"BSXA" link BSXA} operation code. @{b}Pseudocode:@{ub} BSFA,eq $aaaa ;if != gosub $aaaa; ;3,3 BSFA,gt $aaaa ;if <= gosub $aaaa; ;3,3 BSFA,lt $aaaa ;if >= gosub $aaaa; ;3,3 BSFA,eq *$aaaa ;if != gosub *($aaaa); ;3+2,3 BSFA,gt *$aaaa ;if <= gosub *($aaaa); ;3+2,3 BSFA,lt *$aaaa ;if >= gosub *($aaaa); ;3+2,3 @endnode @node BSFR "BSFR" @{b}BRANCH TO SUBROUTINE ON CONDITION FALSE, RELATIVE@{ub} @{b}Addressing Mode:@{ub} Relative @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} BSFR,v (*)a @{b}CALM Mnemonic:@{ub} CALL NE ·+®' CALL NE \@·+®' CALL LE ·+®' CALL LE \@·+®' CALL GE ·+®' CALL GE \@·+®' @{b}Binary Code:@{ub} $B8-$BA @{u}101110vv iaaaaaaa@{uu} 76543210 76543210 v: condition (2 bits) i: indirect addressing flag (1 bit) a: relative address (7 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} SP @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This two-byte conditional subroutine branch instruction causes the processor to perform a subroutine branch only if the two-bit v field does not match the current Condition Code (CC) field in the Program Status Word (PSW). If the fields do not match, the Stack Pointer (SP) is incremented by one and the current contents of the Instruction Address Register (IAR), which points to the location following the second byte of this instruction, is pushed into the Return Address Stack (RAS). The effective address replaces the previous contents of the IAR. If the v field and CC field match, the next instruction is fetched from the location following the second byte of this instruction and the Stack Pointer (SP) is unaffected. Indirect addressing may be specified. The v field may not be coded as $3 as this bit combination (%10111011) is used for the @{"ZBSR" link ZBSR} operation code. @{b}Pseudocode:@{ub} BSFR,eq $aaaa ;if != gosub $aaaa; ;3,2 BSFR,gt $aaaa ;if <= gosub $aaaa; ;3,2 BSFR,lt $aaaa ;if >= gosub $aaaa; ;3,2 BSFR,eq *$aaaa ;if != gosub *($aaaa); ;3+2,2 BSFR,gt *$aaaa ;if <= gosub *($aaaa); ;3+2,2 BSFR,lt *$aaaa ;if >= gosub *($aaaa); ;3+2,2 @endnode @node BSNA "BSNA" @{b}BRANCH TO SUBROUTINE ON REGISTER NON-ZERO, ABSOLUTE@{ub} @{b}Addressing Mode:@{ub} Absolute @{b}Size:@{ub} 3 bytes @{b}Signetics Mnemonic:@{ub} BSNA,r (*)a @{b}CALM Mnemonic:@{ub} CALL rNE m CALL rNE \@m @{b}Binary Code:@{ub} $7C-$7F @{u}011111rr ippaaaaa aaaaaaaa@{uu} 76543210 76543210 76543210 r: register (2 bits) i: indirect addressing flag (1 bit) p: page (2 bits) a: absolute address (13 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} SP @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This three-byte subroutine branch instruction causes the contents of the specified register r to be tested for a non-zero value. If the register contains a non-zero value, the next instruction to be executed is taken from the location pointed to by the effective address. Before replacing the current contents of the Instruction Address Register (IAR) with the effective address, the Stack Pointer (SP) is incremented by one and the address of the byte following the third byte of the instruction is pushed into the Return Address Stack (RAS). If the specified register contains a zero value the next instruction is fetched from the location following the third byte of this instruction. Indirect addressing may be specified. @{b}Pseudocode:@{ub} BSNA,rn $aaaa ;if (rn != 0) gosub $aaaa; ;3,3 BSNA,rn *$aaaa ;if (rn != 0) gosub *($aaaa); ;3+2,3 @endnode @node BSNR "BSNR" @{b}BRANCH TO SUBROUTINE ON REGISTER NON-ZERO, RELATIVE@{ub} @{b}Addressing Mode:@{ub} Relative @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} BSNR,r (*)a @{b}CALM Mnemonic:@{ub} CALL rNE ·+®' CALL rNE \@·+®' @{b}Binary Code:@{ub} $78-$7B @{u}011110rr iaaaaaaa@{uu} 76543210 76543210 r: register (2 bits) i: indirect addressing flag (1 bit) a: relative address (7 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} SP @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This two-byte subroutine branch instruction causes the contents of the specified register r to be tested for a non-zero value. If the register contains a non-zero value, the next instruction to be executed is taken from the location pointed to by the effective address. Before replacing the current contents of the Instruction Address Register (IAR) with the effective address, the Stack Pointer (SP) is incremented by one and the address of the byte following the second byte of the instruction is pushed into the Return Address Stack (RAS). If the specified register contains a zero value the next instruction is fetched from the location following the second byte of this instruction. Indirect addressing may be specified. @{b}Pseudocode:@{ub} BSNR,rn $aaaa ;if (rn != 0) gosub $aaaa; ;3,2 BSNR,rn *$aaaa ;if (rn != 0) gosub *($aaaa); ;3+2,2 @endnode @node BSTA "BSTA" @{b}BRANCH TO SUBROUTINE ON CONDITION TRUE, ABSOLUTE@{ub} @{b}Addressing Mode:@{ub} Absolute @{b}Size:@{ub} 3 bytes @{b}Signetics Mnemonic:@{ub} BSTA,v (*)a @{b}CALM Mnemonic:@{ub} CALL EQ m or CALL AO m CALL EQ \@m or CALL AO \@m CALL GT m CALL GT \@m CALL LT m or CALL NO m CALL LT \@m or CALL NO \@m CALL m CALL \@m @{b}Binary Code:@{ub} $3C-$3F @{u}001111vv ippaaaaa aaaaaaaa@{uu} 76543210 76543210 76543210 v: condition (2 bits) i: indirect addressing flag (1 bit) p: page (2 bits) a: absolute address (13 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} SP @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This three-byte conditional subroutine branch instruction causes the processor to perform a subroutine branch only if the two-bit v field matches the current Condition Code (CC) field in the Program Status Word (PSW). If the fields match, the Stack Pointer (SP) is incremented by one and the current contents of the Instruction Address Register (IAR), which points to the byte following the third byte of this instruction, is pushed into the Return Address Stack (RAS). The effective address replaces the previous contents of the IAR. If the v field and CC field do not match, the next instruction is fetched from the location following the third byte of this instruction and the Stack Pointer (SP) is unaffected. Indirect addressing may be specified. If the v field is set to $3, an unconditional subroutine branch is effected. @{b}Pseudocode:@{ub} BSTA,eq $aaaa ;if == gosub $aaaa; ;3,3 BSTA,gt $aaaa ;if > gosub $aaaa; ;3,3 BSTA,lt $aaaa ;if < gosub $aaaa; ;3,3 BSTA,un $aaaa ;gosub $aaaa; ;3,3 BSTA,eq *$aaaa ;if == gosub *($aaaa); ;3+2,3 BSTA,gt *$aaaa ;if > gosub *($aaaa); ;3+2,3 BSTA,lt *$aaaa ;if < gosub *($aaaa); ;3+2,3 BSTA,un *$aaaa ;gosub *($aaaa); ;5,3 @endnode @node BSTR "BSTR" @{b}BRANCH TO SUBROUTINE ON CONDITION TRUE, RELATIVE@{ub} @{b}Addressing Mode:@{ub} Relative @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} BSTR,v (*)a @{b}CALM Mnemonic:@{ub} CALL EQ ·+®' or CALL AO ·+®' CALL EQ \@·+®' or CALL AO \@·+®' CALL GT ·+®' CALL GT \@·+®' CALL LT ·+®' or CALL NO ·+®' CALL LT \@·+®' or CALL NO \@·+®' CALL ·+®' CALL \@·+®' @{b}Binary Code:@{ub} $38-$3B @{u}001110vv iaaaaaaa@{uu} 76543210 76543210 v: condition (2 bits) i: indirect addressing flag (1 bit) a: relative address (7 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} SP @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This two-byte conditional subroutine branch instruction causes the processor to perform a subroutine branch only if the two-bit v field matches the current Condition Code (CC) field in the Program Status Word (PSW). If the fields match, the Stack Pointer (SP) is incremented by one and the current contents of the Instruction Address Register (IAR), which points to the byte following the second byte of this instruction, is pushed into the Return Address Stack (RAS). The effective address replaces the previous contents of the IAR. If the v field and CC field do not match, the next instruction is fetched from the location following the second byte of this instruction and the Stack Pointer (SP) is unaffected. Indirect addressing may be specified. If the v field is set to $3, an unconditional subroutine branch is effected. @{b}Pseudocode:@{ub} BSTR,eq $aaaa ;if == gosub $aaaa; ;3,2 BSTR,gt $aaaa ;if > gosub $aaaa; ;3,2 BSTR,lt $aaaa ;if < gosub $aaaa; ;3,2 BSTR,un $aaaa ;gosub $aaaa; ;3,2 BSTR,eq *$aaaa ;if == gosub *($aaaa); ;3+2,2 BSTR,gt *$aaaa ;if > gosub *($aaaa); ;3+2,2 BSTR,lt *$aaaa ;if < gosub *($aaaa); ;3+2,2 BSTR,un *$aaaa ;gosub *($aaaa); ;5,2 @endnode @node BSXA "BSXA" @{b}BRANCH TO SUBROUTINE INDEXED, ABSOLUTE@{ub} @{b}Addressing Mode:@{ub} Absolute @{b}Size:@{ub} 3 bytes @{b}Signetics Mnemonic:@{ub} BSXA,r3 (*)a,x @{b}CALM Mnemonic:@{ub} CALL (D)+m CALL (D)+\@m @{b}Binary Code:@{ub} $BF @{u}10111111 ippaaaaa aaaaaaaa@{uu} 76543210 76543210 76543210 i: indirect addressing flag (1 bit) p: page (2 bits) a: absolute address (13 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} SP @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This three-byte branch instruction causes the processor to perform an unconditional subroutine branch. Indexing is required and register #3 must be specified as the index register because the entire first byte of this instruction is decoded by the processor. Execution of this instruction causes the Stack Pointer (SP) to be incremented by one, the address of the byte following the third byte of this instruction is pushed into the Return Address Stack (RAS), and the effective address replaces the contents of the Instruction Address Register (IAR). If indirect addressing is specified, the value in the index register is added to the indirect address to calculate the effective branch address. @{b}Pseudocode:@{ub} BSXA $aaaa,r3 ;gosub $aaaa + r3; ;3,3 BSXA *$aaaa,r3 ;gosub *($aaaa) + r3; ;5,3 @endnode @node BXA "BXA" @{b}BRANCH INDEXED, ABSOLUTE@{ub} @{b}Addressing Mode:@{ub} Absolute @{b}Size:@{ub} 3 bytes @{b}Signetics Mnemonic:@{ub} BXA,r3 (*)a,x @{b}CALM Mnemonic:@{ub} JUMP (D)+m JUMP (D)+\@m @{b}Binary Code:@{ub} $9F @{u}10011111 ippaaaaa aaaaaaaa@{uu} 76543210 76543210 76543210 i: indirect addressing flag (1 bit) p: page (2 bits) a: absolute address (13 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} None @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This three-byte branch instruction causes the processor to perform an unconditional branch. Indexing is required and register #3 must be specified as the index register because the entire first byte of this instruction is decoded by the processor. When executed, the content of the Instruction Address Register (IAR) is replaced by the effective address. If indirect addressing is specified, the value in the index register is added to the indirect address to calculate the effective branch address. @{b}Pseudocode:@{ub} BXA $aaaa,r3 ;goto $aaaa + r3; ;3,3 BXA *$aaaa,r3 ;goto *($aaaa) + r3; ;5,3 @endnode @node COMA "COMA" @{b}COMPARE ABSOLUTE@{ub} @{b}Addressing Mode:@{ub} Absolute @{b}Size:@{ub} 3 bytes @{b}Signetics Mnemonic:@{ub} COMA,r (*)a(,X) @{b}CALM Mnemonic:@{ub} COMP r,m COMP r,\@m COMP A,(r)+m COMP A,(r)+\@m COMP A,(+r)+m COMP A,(+r)+\@m COMP A,(-r)+m COMP A,(-r)+\@m @{b}Binary Code:@{ub} $EC-$EF @{u}111011rr iccaaaaa aaaaaaaa@{uu} 76543210 76543210 76543210 r: register (2 bits) i: indirect addressing flag (1 bit) c: index control bits (2 bits) a: absolute address (13 bits) @{b}Execution Time:@{ub} 4 cycles (12 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}CC1 CC0@{uu} Register r greater than memory byte 0 1 Register r equal to memory byte 0 0 Register r less than memory byte 1 0 @{b}Description:@{ub} This three-byte instruction causes the contents of register r to be compared to the contents of the memory byte pointed to by the effective address. The comparison will be performed in either "arithmetic" or "logical" mode depending on the setting of the COM bit in the Program Status Word (PSW). Where COM=1 (logical mode), the values will be treated as 8-bit, positive binary numbers; when COM=0 (arithmetic mode), the values will be treated as 8-bit, two's complement numbers. Indirect addressing and/or indexing may be specified. If indexing is specified, bits #1 and #0, byte #0, indicate the index register and the destination of the operation implicitly becomes register zero. The execution of this instruction @{i}only@{ui} causes the Condition Code (CC) to be set as in the preceding table. @{b}Pseudocode:@{ub} COMA,rn $aaaa ;compare rn against *($aaaa); ;4,3 COMA,r0 $aaaa,rn ;compare r0 against *($aaaa + rn); ;4,3 COMA,r0 $aaaa,rn+ ;compare r0 against *($aaaa + ++rn); ;4,3 ;or, rn++; compare r0 against *($aaaa + rn); COMA,r0 $aaaa,rn- ;compare r0 against *($aaaa + --rn); ;4,3 ;or, rn--; compare r0 against *($aaaa + rn); COMA,rn *$aaaa ;compare rn against *(*($aaaa)); ;6,3 COMA,r0 *$aaaa,rn ;compare r0 against *(*($aaaa) + rn); ;6,3 COMA,r0 *$aaaa,rn+ ;compare r0 against *(*($aaaa) + ++rn); ;6,3 ;or, rn++; compare r0 against *(*($aaaa) + rn); COMA,r0 *$aaaa,rn- ;compare r0 against *(*($aaaa) + --rn); ;6,3 ;or, rn--; compare r0 against *(*($aaaa) + rn); @endnode @node COMI "COMI" @{b}COMPARE IMMEDIATE@{ub} @{b}Addressing Mode:@{ub} Immediate @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} COMI,r v @{b}CALM Mnemonic:@{ub} COMP r,#n @{b}Binary Code:@{ub} $E4-$E7 @{u}111001rr vvvvvvvv@{uu} 76543210 76543210 r: register (2 bits) v: value (8 bits) @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}CC1 CC0@{uu} Register r greater than v 0 1 Register r equal to v 0 0 Register r less than v 1 0 @{b}Description:@{ub} This two-byte instruction causes the contents of register r to be compared to the contents of the second byte of this instruction. The comparison will be performed in either "arithmetic" or "logical" mode depending on the setting of the COM bit in the Program Status Word (PSW). Where COM=1 (logical mode), the values will be treated as 8-bit, positive binary numbers; when COM=0 (arithmetic mode), the values will be treated as 8-bit, two's complement numbers. The execution of this instruction @{i}only@{ui} causes the Condition Code (CC) to be set as in the preceding table. @{b}Pseudocode:@{ub} COMI,rn $vv ;compare rn against $vv; ;2,2 @endnode @node COMR "COMR" @{b}COMPARE RELATIVE@{ub} @{b}Addressing Mode:@{ub} Relative @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} COMR,r (*)a @{b}CALM Mnemonic:@{ub} COMP r,·+®' COMP r,\@·+®' COMP A,(r)+·+®' COMP A,(r)+\@·+®' COMP A,(+r)+·+®' COMP A,(+r)+\@·+®' COMP A,(-r)+·+®' COMP A,(-r)+\@·+®' @{b}Binary Code:@{ub} $E8-$EB @{u}111010rr iaaaaaaa@{uu} 76543210 76543210 r: register (2 bits) i: indirect addressing flag (1 bit) a: relative address (7 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}CC1 CC0@{uu} Register r greater than memory byte 0 1 Register r equal to memory byte 0 0 Register r less than memory byte 1 0 @{b}Description:@{ub} This two-byte instruction causes the contents of register r to be compared to the contents of the memory byte pointed to by the effective address. The comparison will be performed in either "arithmetic" or "logical" mode depending on the setting of the COM bit in the Program Status Word (PSW). Where COM=1 (logical mode), the values will be treated as 8-bit, positive binary numbers; when COM=0 (arithmetic mode), the values will be treated as 8-bit, two's complement numbers. The execution of this instruction @{i}only@{ui} causes the Condition Code (CC) to be set as in the preceding table. @{b}Pseudocode:@{ub} COMR,rn $aaaa ;compare rn against *($aaaa); ;3,2 COMR,rn *$aaaa ;compare rn against *(*($aaaa)); ;5,2 @endnode @node COMZ "COMZ" @{b}COMPARE TO REGISTER ZERO@{ub} @{b}Addressing Mode:@{ub} Register @{b}Size:@{ub} 1 byte @{b}Signetics Mnemonic:@{ub} COMZ r @{b}CALM Mnemonic:@{ub} COMP A,r @{b}Binary Code:@{ub} $E0-$E3 @{u}111000rr@{uu} 76543210 r: register (2 bits) @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}CC1 CC0@{uu} Register zero greater than register r 0 1 Register zero equal to register r 0 0 Register zero less than register r 1 0 @{b}Description:@{ub} This one-byte instruction causes the contents of the specified register, r, to be compared to the contents of register zero. The comparison will be performed in either "arithmetic" or "logical" mode depending on the setting of the COM bit in the Program Status Word (PSW). Where COM=1 (logical mode), the values will be treated as 8-bit, positive binary numbers; when COM=0 (arithmetic mode), the values will be treated as 8-bit, two's complement numbers. The execution of this instruction @{i}only@{ui} causes the Condition Code (CC) to be set as in the preceding table. @{b}Pseudocode:@{ub} (COMZ r0) COMZ r0 ;CC = EQ; ;2,1 @{b}Pseudocode:@{ub} (all) COMZ rn ;compare r0 against rn; ;2,1 @endnode @node CPSL "CPSL" @{b}CLEAR PROGRAM STATUS LOWER, SELECTIVE@{ub} @{b}Addressing Mode:@{ub} Immediate @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} CPSL v @{b}CALM Mnemonic:@{ub} BIC L,#n CLR CARRY or CLRC CLR LOGICOMP CLR OVERFLOW or CLRV CLR WITHCARRY CLR BANK or CLR BANK1 @{b}Binary Code:@{ub} $75 @{u}01110101 vvvvvvvv@{uu} 76543210 76543210 v: value (8 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} CC, IDC, RS, WC, OVF, COM, C @{b}Condition Code Setting:@{ub} The CC bits may be cleared by the execution of this instruction. @{b}Description:@{ub} This two-byte instruction causes individual bits in the Lower Program Status Byte to be selectively cleared. When this instruction is executed, each bit in the v field of the second byte of this instruction is tested for the presence of a one and if a particular bit in the v field contains a one, the corresponding bit in the status byte is cleared to zero. Any bits in the status byte which are not selected are not modified. @{b}Pseudocode:@{ub} CPSL $vv ;PSL &= ~($vv); ;3,2 @endnode @node CPSU "CPSU" @{b}CLEAR PROGRAM STATUS UPPER, SELECTIVE@{ub} @{b}Addressing Mode:@{ub} Immediate @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} CPSU v @{b}CALM Mnemonic:@{ub} BIC U,#n CLR STACK CLR IOF or ION CLR OUTPUT CLR INPUT @{b}Binary Code:@{ub} $74 @{u}01110100 vvvvvvvv@{uu} 76543210 76543210 v: value (8 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} F, II, SP @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This two-byte instruction causes individual bits in the Upper Program Status Byte to be selectively cleared. When this instruction is executed, each bit in the v field of the second byte of this instruction is tested for the presence of a one and if a particular bit in the v field contains a one, the corresponding bit in the status byte is cleared to zero. Any bits in the status byte which are not selected are not modified. @{b}Pseudocode:@{ub} CPSU $vv ;PSU &= ~($vv & %01100111); ;3,2 @endnode @node DAR "DAR" @{b}DECIMAL ADJUST REGISTER@{ub} @{b}Addressing Mode:@{ub} Register @{b}Size:@{ub} 1 byte @{b}Signetics Mnemonic:@{ub} DAR,r @{b}CALM Mnemonic:@{ub} DA r @{b}Binary Code:@{ub} $94-$97 @{u}100101rr@{uu} 76543210 r: register (2 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} The Condition Code (CC) is set to a meaningless value. @{b}Description:@{ub} This one-byte instruction conditionally adds a decimal ten (two's complement negative six in a four-bit binary number system) to either the high order 4 bits and/or the low order 4 bits of the specified register r. The truth table below indicates the logical operation performed. The operation proceeds based on the contents of the Carry (C) and Interdigit Carry (IDC) bits in the Program Status Word. The C and IDC remain unchanged by the execution of this instruction. This instruction allows BCD sign magnitude arithmetic to be performed on packed digits by the following procedure. BCD Addition: 1. add $66 to augend 2. perform addition of addend and augend 3. perform DAR instruction BCD Subtraction: 1. perform subtraction (2's complement of subtrahend is added to the minuend) 2. perform DAR instruction Since this operation is on sign-magnitude numbers, it is necessary to establish the sign of the result prior to executing in order to properly control the definition of the subtrahend and minuend. @{u}Carry Interdigit Carry Added to Register r@{uu} 0 0 $AA 0 1 $A0 1 1 $00 1 0 $0A @{b}Pseudocode:@{ub} DAR,rn ;rn = BCD(rn); ;3,1 @endnode @node EORA "EORA" @{b}EXCLUSIVE OR ABSOLUTE@{ub} @{b}Addressing Mode:@{ub} Absolute @{b}Size:@{ub} 3 bytes @{b}Signetics Mnemonic:@{ub} EORA,r (*)a(,X) @{b}CALM Mnemonic:@{ub} XOR r,m XOR r,\@m XOR A,(r)+m XOR A,(r)+\@m XOR A,(+r)+m XOR A,(+r)+\@m XOR A,(-r)+m XOR A,(-r)+\@m @{b}Binary Code:@{ub} $2C-$2F @{u}001011rr iccaaaaa aaaaaaaa@{uu} 76543210 76543210 76543210 r: register (2 bits) i: indirect addressing flag (1 bit) c: index control bits (2 bits) a: absolute address (13 bits) @{b}Execution Time:@{ub} 4 cycles (12 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This three-byte instruction causes the contents of register r to be logically Exclusive ORed with the contents of the memory byte pointed to by the effective address. The result of the operation replaces the previous contents of register r. The Exclusive OR operation treats each bit of the argument bytes as in the truth table below: @{u}Bit (0-7) Bit (0-7) Exclusive OR Result@{uu} 0 0 0 0 1 1 1 1 0 1 0 1 Indirect addressing and/or indexing may be specified. If indexing is specified, bits #1 and #0, byte #0, indicate the index register and the destination of the operation implicitly becomes register zero. @{b}Pseudocode:@{ub} EORA,rn $aaaa ;rn ^= *($aaaa); ;4,3 EORA,r0 $aaaa,rn ;r0 ^= *($aaaa + rn); ;4,3 EORA,r0 $aaaa,rn+ ;r0 ^= *($aaaa + ++rn); ;4,3 ;or, rn++; r0 ^= *($aaaa + rn); EORA,r0 $aaaa,rn- ;r0 ^= *($aaaa + --rn); ;4,3 ;or, rn--; r0 ^= *($aaaa + rn); EORA,rn *$aaaa ;rn ^= *(*($aaaa)); ;6,3 EORA,r0 *$aaaa,rn ;r0 ^= *(*($aaaa) + rn); ;6,3 EORA,r0 *$aaaa,rn+ ;r0 ^= *(*($aaaa) + ++rn); ;6,3 ;or, rn++; r0 ^= *(*($aaaa) + rn); EORA,r0 *$aaaa,rn- ;r0 ^= *(*($aaaa) + --rn); ;6,3 ;or, rn--; r0 ^= *(*($aaaa) + rn); @endnode @node EORI "EORI" @{b}EXCLUSIVE OR IMMEDIATE@{ub} @{b}Addressing Mode:@{ub} Immediate @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} EORI,r v @{b}CALM Mnemonic:@{ub} XOR r,#n @{b}Binary Code:@{ub} $24-$27 @{u}011001rr vvvvvvvv@{uu} 76543210 76543210 r: register (2 bits) v: value (8 bits) @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This two-byte instruction causes the contents of register r to be logically Exclusive ORed with the contents of the second byte of this instruction. The result of this operation replaces the contents of register r. The Exclusive OR operation treats each bit of the argument bytes as in the truth table below: @{u}Bit (0-7) Bit (0-7) Exclusive OR Result@{uu} 0 0 0 0 1 1 1 1 0 1 0 1 @{b}Pseudocode:@{ub} EORI,rn $vv ;rn ^= $vv; ;2,2 @endnode @node EORR "EORR" @{b}EXCLUSIVE OR RELATIVE@{ub} @{b}Addressing Mode:@{ub} Relative @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} EORR,r (*)a @{b}CALM Mnemonic:@{ub} XOR r,·+®' XOR r,\@·+®' @{b}Binary Code:@{ub} $28-$2B @{u}001010rr iaaaaaaa@{uu} 76543210 76543210 r: register (2 bits) i: indirect addressing flag (1 bit) a: relative address (7 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This two-byte instruction causes the contents of register r to be logically Exclusive ORed with the contents of the memory byte pointed to by the effective address. The result of this operation replaces the previous contents of register r. Indirect indexing may be specified. The Exclusive OR operation treats each bit of the argument bytes as in the truth table below: @{u}Bit (0-7) Bit (0-7) Exclusive OR Result@{uu} 0 0 0 0 1 1 1 1 0 1 0 1 @{b}Pseudocode:@{ub} EORR,rn $aaaa ;rn ^= *($aaaa); ;3,2 EORR,rn *$aaaa ;rn ^= *(*($aaaa)); ;5,2 @endnode @node EORZ "EORZ" @{b}EXCLUSIVE OR TO REGISTER ZERO@{ub} @{b}Addressing Mode:@{ub} Register @{b}Size:@{ub} 1 byte @{b}Signetics Mnemonic:@{ub} EORZ r @{b}CALM Mnemonic:@{ub} XOR A,r @{b}Binary Code:@{ub} $20-$23 @{u}001000rr@{uu} 76543210 r: register (2 bits) @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This one-byte instruction causes the contents of the specified register, r, to be logically Exclusive ORed with the contents of register zero. The result of the operation replaces the contents of register zero. The contents of register r remain unchanged. The Exclusive OR operation treats each bit of the argument bytes as in the truth table below: @{u}Bit (0-7) Bit (0-7) Inclusive OR Result@{uu} 0 0 0 0 1 1 1 1 0 1 0 1 @{b}Pseudocode:@{ub} EORZ rn ;r0 ^= rn; ;2,1 @endnode @node HALT "HALT" @{b}HALT, ENTER WAIT STATE@{ub} @{b}Addressing Mode:@{ub} Implicit @{b}Size:@{ub} 1 byte @{b}Signetics Mnemonic:@{ub} HALT @{b}CALM Mnemonic:@{ub} WAIT @{b}Binary Code:@{ub} $40 @{u}01000000@{uu} 76543210 @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} None @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This one-byte instruction causes the processor to stop executing instructions and enter the WAIT state. The RUN/WAIT line is set to the WAIT state. The only way to enter the RUN state after a HALT has been executed is to reset the 2650 or to interrupt the processor. @{b}Pseudocode:@{ub} HALT ;for (;;); ;2,1 @endnode @node IORA "IORA" @{b}INCLUSIVE OR ABSOLUTE@{ub} @{b}Addressing Mode:@{ub} Absolute @{b}Size:@{ub} 3 bytes @{b}Signetics Mnemonic:@{ub} IORA,r (*)a(,X) @{b}CALM Mnemonic:@{ub} OR r,m OR r,\@m OR A,(r)+m OR A,(r)+\@m OR A,(+r)+m OR A,(+r)+\@m OR A,(-r)+m OR A,(-r)+\@m @{b}Binary Code:@{ub} $6C-$6F @{u}011011rr iccaaaaa aaaaaaaa@{uu} 76543210 76543210 76543210 r: register (2 bits) i: indirect addressing flag (1 bit) c: index control bits (2 bits) a: absolute address (13 bits) @{b}Execution Time:@{ub} 4 cycles (12 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This three-byte instruction causes the contents of register r to be logically Inclusive ORed with the contents of the memory byte pointed to by the effective address. The result of the operation replaces the previous contents of register r. The Inclusive OR operation treats each bit of the argument bytes as in the truth table below: @{u}Bit (0-7) Bit (0-7) Inclusive OR Result@{uu} 0 0 0 0 1 1 1 1 1 1 0 1 Indirect addressing and/or indexing may be specified. If indexing is specified, bits #1 and #0, byte #0, indicate the index register and the destination of the operation implicitly becomes register zero. @{b}Pseudocode:@{ub} IORA,rn $aaaa ;rn |= *($aaaa); ;4,3 IORA,r0 $aaaa,rn ;r0 |= *($aaaa + rn); ;4,3 IORA,r0 $aaaa,rn+ ;r0 |= *($aaaa + ++rn); ;4,3 ;or, rn++; r0 |= *($aaaa + rn); IORA,r0 $aaaa,rn- ;r0 |= *($aaaa + --rn); ;4,3 ;or, rn--; r0 |= *($aaaa + rn); IORA,rn *$aaaa ;rn |= *(*($aaaa)); ;6,3 IORA,r0 *$aaaa,rn ;r0 |= *(*($aaaa) + rn); ;6,3 IORA,r0 *$aaaa,rn+ ;r0 |= *(*($aaaa) + ++rn); ;6,3 ;or, rn++; r0 |= *(*($aaaa) + rn); IORA,r0 *$aaaa,rn- ;r0 |= *(*($aaaa) + --rn); ;6,3 ;or, rn--; r0 |= *(*($aaaa) + rn); @endnode @node IORI "IORI" @{b}INCLUSIVE OR IMMEDIATE@{ub} @{b}Addressing Mode:@{ub} Immediate @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} IORI,r v @{b}CALM Mnemonic:@{ub} OR r,#n @{b}Binary Code:@{ub} $64-$67 @{u}011001rr vvvvvvvv@{uu} 76543210 76543210 r: register (2 bits) v: value (8 bits) @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This two-byte instruction causes the contents of register r to be logically Inclusive ORed with the contents of the second byte of this instruction. The result of this operation replaces the contents of register r. The Inclusive OR operation treats each bit of the argument bytes as in the truth table below: @{u}Bit (0-7) Bit (0-7) Inclusive OR Result@{uu} 0 0 0 0 1 1 1 1 1 1 0 1 @{b}Pseudocode:@{ub} IORI,rn $vv ;rn |= $vv; ;2,2 @endnode @node IORR "IORR" @{b}INCLUSIVE OR RELATIVE@{ub} @{b}Addressing Mode:@{ub} Relative @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} IORR,r (*)a @{b}CALM Mnemonic:@{ub} OR r,·+®' OR r,\@·+®' @{b}Binary Code:@{ub} $68-$6B @{u}011010rr iaaaaaaa@{uu} 76543210 76543210 r: register (2 bits) i: indirect addressing flag (1 bit) a: relative address (7 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This two-byte instruction causes the contents of register r to be logically Inclusive ORed with the contents of the memory byte pointed to by the effective address. The result of this operation replaces the previous contents of register r. Indirect indexing may be specified. The Inclusive OR operation treats each bit of the argument bytes as in the truth table below: @{u}Bit (0-7) Bit (0-7) Inclusive OR Result@{uu} 0 0 0 0 1 1 1 1 1 1 0 1 @{b}Pseudocode:@{ub} IORR,rn $aaaa ;rn |= *($aaaa); ;3,2 IORR,rn *$aaaa ;rn |= *(*($aaaa)); ;5,2 @endnode @node IORZ "IORZ" @{b}INCLUSIVE OR TO REGISTER ZERO@{ub} @{b}Addressing Mode:@{ub} Register @{b}Size:@{ub} 1 byte @{b}Signetics Mnemonic:@{ub} IORZ r @{b}CALM Mnemonic:@{ub} OR A,r @{b}Binary Code:@{ub} $60-$63 @{u}011000rr@{uu} 76543210 r: register (2 bits) @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This one-byte instruction causes the contents of the specified register, r, to be logically Inclusive ORed with the contents of register zero. The result of the operation replaces the contents of register zero. The contents of register r remain unchanged. The Inclusive OR operation treats each bit of the argument bytes as in the truth table below: @{u}Bit (0-7) Bit (0-7) Inclusive OR Result@{uu} 0 0 0 0 1 1 1 1 1 1 0 1 @{b}Pseudocode:@{ub} IORZ rn ;r0 |= rn; ;2,1 @endnode @node LDPL "LDPL" @{b}LOAD PROGRAM STATUS, LOWER from memory@{ub} (2650-B only) @{b}Addressing Mode:@{ub} Absolute @{b}Size:@{ub} 3 bytes @{b}Signetics Mnemonic:@{ub} LDPL (*)a @{b}CALM Mnemonic:@{ub} LOAD L,m LOAD L,\@m @{b}Binary Code:@{ub} $10 @{u}00010000 ippaaaaa aaaaaaaa@{uu} 76543210 76543210 76543210 Byte 0 Byte 1 Byte 2 i: indirect addressing flag p: page a: address @{b}Execution Time:@{ub} 4 cycles (12 clock periods) @{b}Processor Registers Affected:@{ub} CC, IDC, RS, WC, OVF, COM, C @{b}Condition Code Setting:@{ub} The CC will take on the value in bits #7 and #6 of the byte pointed to by the effective address. @{b}Description:@{ub} This three-byte instruction causes the current contents of the Lower Program Status Byte to be replaced with the contents of the byte of memory pointed to by the effective address. See @{"Program Status Word" link Orga2} description for bit assignments. @{b}Pseudocode:@{ub} LDPL $aaaa ;PSL = *($aaaa); ;4,3 LDPL *$aaaa ;PSL = *(*($aaaa)); ;4,3 @endnode @node LODA "LODA" @{b}LOAD ABSOLUTE@{ub} @{b}Addressing Mode:@{ub} Absolute @{b}Size:@{ub} 3 bytes @{b}Signetics Mnemonic:@{ub} LODA,r (*)a(,X) @{b}CALM Mnemonic:@{ub} LOAD r,m LOAD r,\@m LOAD A,(r)+m LOAD A,(r)+\@m LOAD A,(+r)+m LOAD A,(+r)+\@m LOAD A,(-r)+m LOAD A,(-r)+\@m @{b}Binary Code:@{ub} $0C-$0F @{u}000011rr iccaaaaa aaaaaaaa@{uu} 76543210 76543210 76543210 r: register (2 bits) i: indirect addressing flag (1 bit) c: index control bits (2 bits) a: absolute address (13 bits) @{b}Execution Time:@{ub} 4 cycles (12 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This three-byte instruction transfers a byte of data from memory into the specified register, r. The data byte is found at the effective address. If indexing is specified, bits #1 and #0, byte #0, indicate the index register and the destination of the operation implicitly becomes register zero. The previous contents of register r are lost. Indirect addressing and/or indexing may be specified. @{b}Pseudocode:@{ub} LODA,rn $aaaa ;rn = *($aaaa); ;4,3 LODA,r0 $aaaa,rn ;r0 = *($aaaa + rn); ;4,3 LODA,r0 $aaaa,rn+ ;r0 = *($aaaa + ++rn); ;4,3 ;or, rn++; r0 = *($aaaa + rn); LODA,r0 $aaaa,rn- ;r0 = *($aaaa + --rn); ;4,3 ;or, rn--; r0 = *($aaaa + rn); LODA,rn *$aaaa ;rn = *(*($aaaa)); ;6,3 LODA,r0 *$aaaa,rn ;r0 = *(*($aaaa) + rn); ;6,3 LODA,r0 *$aaaa,rn+ ;r0 = *(*($aaaa) + ++rn); ;6,3 ;or, rn++; r0 = *(*($aaaa) + rn); LODA,r0 *$aaaa,rn- ;r0 = *(*($aaaa) + --rn); ;6,3 ;or, rn--; r0 = *(*($aaaa) + rn); @endnode @node LODI "LODI" @{b}LOAD IMMEDIATE@{ub} @{b}Addressing Mode:@{ub} Immediate @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} LODI,r v @{b}CALM Mnemonic:@{ub} LOAD r,#n @{b}Binary Code:@{ub} $04-$07 @{u}000001rr vvvvvvvv@{uu} 76543210 76543210 r: register (2 bits) v: value (8 bits) @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This two-byte instruction transfers the second byte of the instruction, v, into the specified register, r. The previous contents of r are lost. @{b}Pseudocode:@{ub} LODI,rn $vv ;rn = $vv; ;2,2 @endnode @node LODR "LODR" @{b}LOAD RELATIVE@{ub} @{b}Addressing Mode:@{ub} Relative @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} LODR,r (*)a @{b}CALM Mnemonic:@{ub} LOAD r,·+®' LOAD r,\@·+®' @{b}Binary Code:@{ub} $08-$0B @{u}000010rr iaaaaaaa@{uu} 76543210 76543210 r: register (2 bits) i: indirect addressing flag (1 bit) a: relative address (7 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This two-byte instruction transfers a byte of data from memory into the specified register, r. The data byte is found at the effective address formed by the addition of the a field and the address of the byte following this instruction. The previous contents of register r are lost. Indirect addressing may be specified. @{b}Pseudocode:@{ub} LODR,rn $aaaa ;rn = *($aaaa); ;3,2 LODR,rn *$aaaa ;rn = *(*($aaaa)); ;5,2 @endnode @node LODZ "LODZ" @{b}LOAD REGISTER ZERO@{ub} @{b}Addressing Mode:@{ub} Register @{b}Size:@{ub} 1 byte @{b}Signetics Mnemonic:@{ub} LODZ r @{b}CALM Mnemonic:@{ub} LOAD A,r @{b}Binary Code:@{ub} $01-$03 @{u}000000rr@{uu} 76543210 r: register (2 bits) @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This one-byte instruction transfers the contents of the specified register, r, into register zero. The previous contents of register zero are lost. The contents of register r remain unchanged. When the specified register, r, equals 0, the operation code is changed to @{"$60" link IORZ} by the assembler. The instruction, %00000000, yields indeterminate results. @{b}Pseudocode:@{ub} LODZ rn ;r0 = rn; ;2,1 @endnode @node LPSL "LPSL" @{b}LOAD PROGRAM STATUS, LOWER from register zero@{ub} @{b}Addressing Mode:@{ub} Immediate @{b}Size:@{ub} 1 byte @{b}Signetics Mnemonic:@{ub} LPSL @{b}CALM Mnemonic:@{ub} LOAD A,L @{b}Binary Code:@{ub} $93 @{u}10010011@{uu} 76543210 @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} CC, IDC, RS, WC, OVF, COM, C @{b}Condition Code Setting:@{ub} The CC will take on the value in bits #7 and #6 of register zero. @{b}Description:@{ub} This one-byte instruction causes the current contents of the Lower Program Status Byte to be replaced with the contents of register zero. See @{"Program Status Word" link Orga2} description for bit assignments. @{b}Pseudocode:@{ub} LPSL ;PSL = r0; ;2,1 @endnode @node LPSU "LPSU" @{b}LOAD PROGRAM STATUS, UPPER from register zero@{ub} @{b}Addressing Mode:@{ub} Immediate @{b}Size:@{ub} 1 byte @{b}Signetics Mnemonic:@{ub} LPSU @{b}CALM Mnemonic:@{ub} LOAD A,U @{b}Binary Code:@{ub} $92 @{u}10010010@{uu} 76543210 @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} F, II, SP @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This one-byte instruction causes the current contents of the Upper Program Status Byte to be replaced with the contents of register zero. See @{"Program Status Word" link Orga2} description for bit assignments. Bits #4 and #3 of the PSU are unassigned and will always be regarded as containing zeroes. @{b}Pseudocode:@{ub} LPSU ;PSU = (r0 & %01100111); ;2,1 @endnode @node NOP "NOP" @{b}NO OPERATION@{ub} @{b}Addressing Mode:@{ub} Implicit @{b}Size:@{ub} 1 byte @{b}Signetics Mnemonic:@{ub} NOP @{b}CALM Mnemonic:@{ub} NOP @{b}Binary Code:@{ub} $C0 @{u}11000000@{uu} 76543210 @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} None @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This one-byte instruction causes the processor to take no action upon decoding it. No registers are changed, but fetching and executing a NOP instruction requires two processor cycles. @{b}Pseudocode:@{ub} NOP ;; ;2,1 @endnode @node PPSL "PPSL" @{b}PRESET PROGRAM STATUS LOWER, SELECTIVE@{ub} @{b}Addressing Mode:@{ub} Immediate @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} PPSL v @{b}CALM Mnemonic:@{ub} OR L,#n SET CARRY or SETC SET LOGICOMP SET OVERFLOW or SETV SET WITHCARRY SET BANK or SET BANK1 @{b}Binary Code:@{ub} $77 @{u}01110111 vvvvvvvv@{uu} 76543210 76543210 v: value (8 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} CC, IDC, RS, WC, OVF, COM, C @{b}Condition Code Setting:@{ub} The CC bits may be cleared by the execution of this instruction. @{b}Description:@{ub} This two-byte instruction causes individual bits in the Lower Program Status Byte to be selectively set to binary one. When this instruction is executed, each bit in the v field of the second byte of this instruction is tested for the presence of a one and if a particular bit in the v field contains a one, the corresponding bit in the status byte is set to binary one. Any bits in the status byte which are not selected are not modified. @{b}Pseudocode:@{ub} PPSL $vv ;PSL |= $vv; ;3,2 @endnode @node PPSU "PPSU" @{b}PRESET PROGRAM STATUS UPPER, SELECTIVE@{ub} @{b}Addressing Mode:@{ub} Immediate @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} PPSU v @{b}CALM Mnemonic:@{ub} OR U,#n SET STACK SET IOF or IOF SET OUTPUT SET INPUT @{b}Binary Code:@{ub} $76 @{u}01110110 vvvvvvvv@{uu} 76543210 76543210 v: value (8 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} F, II, SP @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This two-byte instruction causes individual bits in the Upper Program Status Byte to be selectively set to binary one. When this instruction is executed, each bit in the v field of the second byte of this instruction is tested for the presence of a one and if a particular bit in the v field contains a one, the corresponding bit in the status byte is set to binary one. Any bits in the status byte which are not selected are not modified. @{b}Pseudocode:@{ub} PPSU $vv ;PSU |= ($vv & %01100111); ;3,2 @endnode @node REDC "REDC" @{b}READ CONTROL@{ub} @{b}Addressing Mode:@{ub} Register @{b}Size:@{ub} 1 byte @{b}Signetics Mnemonic:@{ub} REDC,r @{b}CALM Mnemonic:@{ub} LOAD r,$CTRL @{b}Binary Code:@{ub} $30-$33 @{u}001100rr@{uu} 76543210 r: register (2 bits) @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This one-byte input instruction causes a byte of data to be transferred from the data bus into register r. Signals on the data bus are considered to be true signals, ie. a high level will be set into the register as a one. When executing this instruction, the processor raises the Operation Request (OPREQ) line, simultaneously switching the M/IO line to IO, the R/W line to R (Read), the D/C line to C (Control), and the E/NE line to NE (Non-extended). @{b}Pseudocode:@{ub} REDC,rn ;rn = *(CONTROLBUS); ;3,2 @endnode @node REDD "REDD" @{b}READ DATA@{ub} @{b}Addressing Mode:@{ub} Register @{b}Size:@{ub} 1 byte @{b}Signetics Mnemonic:@{ub} REDD,r @{b}CALM Mnemonic:@{ub} LOAD r,$DATA @{b}Binary Code:@{ub} $70-$73 @{u}011100rr@{uu} 76543210 r: register (2 bits) @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This one-byte input instruction causes a byte of data to be transferred from the data bus into register r. Signals on the data bus are considered to be true signals, ie. a high level will be set into the register as a one. When executing this instruction, the processor raises the Operation Request (OPREQ) line, simultaneously switching the M/IO line to IO and the R/W line to R (Read). Also, during the OPREQ signal, the D/C line switches to D (Data), and the E/NE line to NE (Non-extended). @{b}Pseudocode:@{ub} REDD,rn ;rn = *(DATABUS); ;3,2 @endnode @node REDE "REDE" @{b}READ EXTENDED@{ub} @{b}Addressing Mode:@{ub} Immediate @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} REDE,r v @{b}CALM Mnemonic:@{ub} LOAD r,$n @{b}Binary Code:@{ub} $54-$57 @{u}010101rr vvvvvvvv@{uu} 76543210 76543210 r: register (2 bits) v: value (8 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This two-byte input instruction causes a byte of data to be transferred from the data bus into register r. During the execution of this instruction, the content of the second byte of this instruction is made available on the address bus. Signals on the data bus are true signals, ie. a high levels is interpreted as a one. During execution, the processor raises the Operation Request (OPREQ) line, simultaneously placing the contents of the second byte of the instruction on the address bus. During the OPREQ signal, the M/IO line is switched to IO, the R/W line to R (Read), the E/NE line to E (Extended). @{b}Pseudocode:@{ub} REDE,rn $vv ;*(ADDRESSBUS) = $vv; rn = *(DATABUS); ;3,2 @endnode @node RETC "RETC" @{b}RETURN FROM SUBROUTINE, CONDITIONAL@{ub} @{b}Addressing Mode:@{ub} Register @{b}Size:@{ub} 1 byte @{b}Signetics Mnemonic:@{ub} RETC,v @{b}CALM Mnemonic:@{ub} RET EQ or RET AO RET GT RET LT or RET NO RET @{b}Binary Code:@{ub} $14-$17 @{u}000101vv@{uu} 76543210 v: condition (2 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} SP @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This one-byte instruction is used by a subroutine to conditionally effect a return of control to the program which last issued a subroutine branch instruction. If the two-bit v field in the instruction matches the Condition Code (CC) field in the Program Status Word, the following action is taken: The address contained in the top of the Return Address Stack (RAS) replaces the previous contents of the Instruction Address Register (IAR), and the Stack Pointer (SP) is decremented by one. If the v field does not match CC, the return is not effected and the next instruction to be executed is taken from the location following this instruction. If v is specified as $3, the return is executed unconditionally. @{b}Pseudocode:@{ub} RETC,eq ;if == return; ;3,1 RETC,gt ;if > return; ;3,1 RETC,lt ;if < return; ;3,1 RETC,un ;return; ;3,1 @endnode @node RETE "RETE" @{b}RETURN FROM SUBROUTINE AND ENABLE INTERRUPT, CONDITIONAL@{ub} @{b}Addressing Mode:@{ub} Implicit @{b}Size:@{ub} 1 byte @{b}Signetics Mnemonic:@{ub} RETE,v @{b}CALM Mnemonic:@{ub} RETION EQ or RETION AO RETION GT RETION LT or RETION NO RETION @{b}Binary Code:@{ub} $34-$37 @{u}001101vv@{uu} 76543210 v: condition (2 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} SP, II @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This one-byte instruction is used by a subroutine to conditionally effect a return of control to the program which last issued a subroutine branch instruction. Additionally, if the return is effected, the Interrupt Inhibit (II) bit in the Program Status Word is cleared to zero, thus enabling interrupts. This instruction is mainly intended to be used by an interrupt handling routine because receipt of an interrupt causes a subroutine branch to be effected and the Interrupt Inhibit (II) bit to be set to 1. The interrupt handling routine must be able to return and enable simultaneously so that the interrupt routine cannot be interrupted unless that is specifically desired. If the two-bit v field in the instruction matched the Condition Code (CC) field in the Program Status Word (PSW), the following action is taken: The address contained in the top of the Return Address Stack (RAS) replaces the previous contents of the Instruction Address Register (IAR), the Stack Pointer (SP) is decremented by one and the II bit is cleared to zero. If the v field does not match CC, the return is not effected and the next instruction to be executed is taken from the location following this instruction. If v is specified as $3, the return is executed unconditionally. @{b}Pseudocode:@{ub} RETE,eq ;if == then { PSU &= ~PSU_II; return; } ;3,1 RETE,gt ;if > then { PSU &= ~PSU_II; return; } ;3,1 RETE,lt ;if < then { PSU &= ~PSU_II; return; } ;3,1 RETE,un ;PSU &= ~PSU_II; return; ;3,1 @endnode @node RRL "RRL" @{b}ROTATE REGISTER LEFT@{ub} @{b}Addressing Mode:@{ub} Register @{b}Size:@{ub} 1 byte @{b}Signetics Mnemonic:@{ub} RRL,r @{b}CALM Mnemonic:@{ub} RL r RLC r @{b}Binary Code:@{ub} $D0-$D3 @{u}110100rr@{uu} 76543210 r: register (2 bits) @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} C, CC, IDC, OVF @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This one-byte instruction causes the contents of the specified register, r, to be shifted left one bit. If the WC bit in the Program Status Word (PSW) is set to zero, bit #7 of register r flows into bit #0; if WC=1, then bit #7 flows into the Carry (C) bit and the Carry (C) bit flows into bit #0. Register bit #4 flows into the IDC if WC=1. +------------------------------------+ | +-----+ | | | IDC | (NOT CHANGED) | | +-----+ | +---+ | +------------------------------+ | | C | +--+ 7 < 6 < 5 < 4 < 3 < 2 < 1 < 0<--+ WC=0 +---+ +------------------------------+ +----------------------------------------------+ | +-----+ | | | IDC <-+ | | +-----+ | | | +---+ +-------------+----------------+ | +--+ C <-----+ 7 < 6 < 5 < 4 < 3 < 2 < 1 < 0<--+ WC=1 +---+ +------------------------------+ @{b}Note:@{ub} Whenever a rotate causes bit #7 of the specified register to change polarity, the OVF bit is set in the PSL. @{b}Pseudocode:@{ub} RRL,rn ;rn <<= 1; ;2,1 @endnode @node RRR "RRR" @{b}ROTATE REGISTER RIGHT@{ub} @{b}Addressing Mode:@{ub} Register @{b}Size:@{ub} 1 byte @{b}Signetics Mnemonic:@{ub} RRR,r @{b}CALM Mnemonic:@{ub} RR r RRC r @{b}Binary Code:@{ub} $50-$53 @{u}010100rr@{uu} 76543210 r: register (2 bits) @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} C, CC, IDC, OVF @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This one-byte instruction causes the contents of the specified register, r, to be shifted right one bit. If the WC bit in the Program Status Word (PSW) is set to zero, bit #0 of register r flows into bit #7; if WC=1, then bit #0 flows into the Carry (C) bit and the Carry (C) bit flows into bit #7. Register bit #6 flows into the IDC if WC=1. +------------------------------------+ | +-----+ | | | IDC | (NOT CHANGED) | | +-----+ | +---+ | +------------------------------+ | | C | +--> 7 > 6 > 5 > 4 > 3 > 2 > 1 > 0+--+ WC=0 +---+ +------------------------------+ +----------------------------------------------+ | +-----+ | | +-> IDC | | | | +-----+ | | +---+ +-----+-------+----------------+ | +--> C +-----> 7 > 6 > 5 > 4 > 3 > 2 > 1 > 0+--+ WC=1 +---+ +------------------------------+ @{b}Note:@{ub} Whenever a rotate causes bit #7 of the specified register to change polarity, the OVF bit is set in the PSL. @{b}Pseudocode:@{ub} RRR,rn ;rn >>= 1; ;2,1 @endnode @node SPSL "SPSL" @{b}STORE PROGRAM STATUS, LOWER to register zero@{ub} @{b}Addressing Mode:@{ub} Immediate @{b}Size:@{ub} 1 byte @{b}Signetics Mnemonic:@{ub} SPSL @{b}CALM Mnemonic:@{ub} LOAD A,L @{b}Binary Code:@{ub} $13 @{u}00010011@{uu} 76543210 @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This one-byte instruction causes the current contents of the Lower Program Status Byte to be transferred into register zero. See @{"Program Status Word" link Orga2} description for bit assignments. @{b}Pseudocode:@{ub} SPSL ;r0 = PSL; ;2,1 @endnode @node SPSU "SPSU" @{b}STORE PROGRAM STATUS, UPPER to register zero@{ub} @{b}Addressing Mode:@{ub} Immediate @{b}Size:@{ub} 1 byte @{b}Signetics Mnemonic:@{ub} SPSU @{b}CALM Mnemonic:@{ub} LOAD A,U @{b}Binary Code:@{ub} $12 @{u}00010010@{uu} 76543210 @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This one-byte instruction causes the current contents of the Upper Program Status Byte to be transferred into register zero. See @{"Program Status Word" link Orga2} description for bit assignments. Bits #4 and #3 which are unassigned will always be stored as zeroes. @{b}Pseudocode:@{ub} SPSU ;r0 = PSU; ;2,1 @endnode @node STPL "STPL" @{b}STORE PROGRAM STATUS, LOWER to memory@{ub} (2650-B only) @{b}Addressing Mode:@{ub} Absolute @{b}Size:@{ub} 3 bytes @{b}Signetics Mnemonic:@{ub} STPL (*)a @{b}CALM Mnemonic:@{ub} LOAD m,L LOAD \@m,L @{b}Binary Code:@{ub} $11 @{u}00010001 ippaaaaa aaaaaaaa@{uu} 76543210 76543210 76543210 Byte 0 Byte 1 Byte 2 i: indirect addressing flag p: page a: address @{b}Execution Time:@{ub} 4 cycles (12 clock periods) @{b}Processor Registers Affected:@{ub} None @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This three-byte instruction causes the current contents of the Lower Program Status Byte to be transferred into the byte of memory pointed to by the effective address. See @{"Program Status Word" link Orga2} description for bit assignments. @{b}Pseudocode:@{ub} STPL $aaaa ;*($aaaa) = PSL; ;4,3 STPL *$aaaa ;*(*($aaaa)) = PSL; ;4,3 @endnode @node STRA "STRA" @{b}STORE ABSOLUTE@{ub} @{b}Addressing Mode:@{ub} Absolute @{b}Size:@{ub} 3 bytes @{b}Signetics Mnemonic:@{ub} STRA,r (*)a(,X) @{b}CALM Mnemonic:@{ub} LOAD m,r LOAD \@m,r LOAD (r)+m,A LOAD (r)+\@m,A LOAD (+r)+m,A LOAD (+r)+\@m,A LOAD (-r)+m,A LOAD (-r)+\@m,A @{b}Binary Code:@{ub} $CC-$CF @{u}110011rr iccaaaaa aaaaaaaa@{uu} 76543210 76543210 76543210 r: register (2 bits) i: indirect addressing flag (1 bit) c: index control bits (2 bits) a: absolute address (13 bits) @{b}Execution Time:@{ub} 4 cycles (12 clock periods) @{b}Processor Registers Affected:@{ub} None @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This three-byte instruction transfers a byte of data from the specified register, r, into the byte of memory pointed to by the effective address. The contents of register r remain unchanged and the contents of the memory byte are replaced. Indirect addressing and/or indexing may be specified. If indexing is specified, bits #1 and #0, byte #0, indicate the index register and the destination of the operation implicitly becomes register zero. @{b}Pseudocode:@{ub} STRA,rn $aaaa ;*($aaaa) = rn; ;4,3 STRA,r0 $aaaa,rn ;*($aaaa + rn) = r0; ;4,3 STRA,r0 $aaaa,rn+ ;*($aaaa + ++rn) = r0; ;4,3 ;or, rn++; *($aaaa + rn) = r0; STRA,r0 $aaaa,rn- ;*($aaaa + --rn) = r0; ;4,3 ;or, rn--; *($aaaa + rn) = r0; STRA,rn *$aaaa ;*(*($aaaa)) = rn; ;6,3 STRA,r0 *$aaaa,rn ;*(*($aaaa) + rn) = r0; ;6,3 STRA,r0 *$aaaa,rn+ ;*(*($aaaa) + ++rn) = r0; ;6,3 ;or, rn++; *(*($aaaa) + rn) = r0; STRA,r0 *$aaaa,rn- ;*(*($aaaa) + --rn) = r0; ;6,3 ;or, rn--; *(*($aaaa) + rn) = r0; @endnode @node STRR "STRR" @{b}STORE RELATIVE@{ub} @{b}Addressing Mode:@{ub} Relative @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} STRR,r (*)a @{b}CALM Mnemonic:@{ub} LOAD ·+®',r LOAD \@·+®',r @{b}Binary Code:@{ub} $C8-$CB @{u}110010rr iaaaaaaa@{uu} 76543210 76543210 r: register (2 bits) i: indirect addressing flag (1 bit) a: relative address (7 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} None @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This two-byte instruction transfers a byte of data from the specified register, r, into the byte of memory pointed to by the effective address. The contents of register r remain unchanged and the contents of the memory byte are replaced. Indirect addressing may be specified. @{b}Pseudocode:@{ub} STRR,rn $aaaa ;*($aaaa) = rn; ;3,2 STRR,rn *$aaaa ;*(*($aaaa)) = rn; ;5,2 @endnode @node STRZ "STRZ" @{b}STORE REGISTER ZERO@{ub} @{b}Addressing Mode:@{ub} Register @{b}Size:@{ub} 1 byte @{b}Signetics Mnemonic:@{ub} STRZ r @{b}CALM Mnemonic:@{ub} LOAD r,A @{b}Binary Code:@{ub} $C1-$C3 @{u}110000rr@{uu} 76543210 r: register (2 bits) @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This one-byte instruction transfers the contents of register zero into the specified register, r. The previous contents of register r are lost. The contents of register zero remain unchanged. @{b}Description:@{ub} Register r may not be specified as zero. This operation code, %11000000, is reserved for @{"NOP" link NOP}. @{b}Pseudocode:@{ub} STRZ rn ;rn = r0; ;2,1 @endnode @node SUBA "SUBA" @{b}SUBTRACT ABSOLUTE@{ub} @{b}Addressing Mode:@{ub} Absolute @{b}Size:@{ub} 3 bytes @{b}Signetics Mnemonic:@{ub} SUBA,r (*)a(,X) @{b}CALM Mnemonic:@{ub} SUB r,m SUB r,\@m SUB A,(r)+m SUB A,(r)+\@m SUB A,(+r)+m SUB A,(+r)+\@m SUB A,(-r)+m SUB A,(-r)+\@m SUBB r,m SUBB r,\@m SUBB A,(r)+m SUBB A,(r)+\@m SUBB A,(+r)+m SUBB A,(+r)+\@m SUBB A,(-r)+m SUBB A,(-r)+\@m @{b}Binary Code:@{ub} $AC-$AF @{u}101011rr iccaaaaa aaaaaaaa@{uu} 76543210 76543210 76543210 r: register (2 bits) i: indirect addressing flag (1 bit) c: index control bits (2 bits) a: absolute address (13 bits) @{b}Execution Time:@{ub} 4 cycles (12 clock periods) @{b}Processor Registers Affected:@{ub} C, CC, IDC, OVF @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This three-byte instruction causes the contents of the byte of memory pointed to by the effective address to be subtracted from the contents of register r. The result of the subtraction replaces the contents of register r. The subtraction is performed by taking the binary two's complement of the contents of the memory byte and adding that result to the contents of register r. Indirect addressing and/or indexing may be specified. If indexing is specified, bits #1 and #0, byte #0, indicate the index register and the destination of the operation implicitly becomes register zero. @{b}Note:@{ub} Subtract with Borrow may be effected. See Carry (C) bit. @{b}Pseudocode:@{ub} SUBA,rn $aaaa ;rn -= *($aaaa); ;4,3 SUBA,r0 $aaaa,rn ;r0 -= *($aaaa + rn); ;4,3 SUBA,r0 $aaaa,rn+ ;r0 -= *($aaaa + ++rn); ;4,3 ;or, rn++; r0 -= *($aaaa + rn); SUBA,r0 $aaaa,rn- ;r0 -= *($aaaa + --rn); ;4,3 ;or, rn--; r0 -= *($aaaa + rn); SUBA,rn *$aaaa ;rn -= *(*($aaaa)); ;6,3 SUBA,r0 *$aaaa,rn ;r0 -= *(*($aaaa) + rn); ;6,3 SUBA,r0 *$aaaa,rn+ ;r0 -= *(*($aaaa) + ++rn); ;6,3 ;or, rn++; r0 -= *(*($aaaa) + rn); SUBA,r0 *$aaaa,rn- ;r0 -= *(*($aaaa) + --rn); ;6,3 ;or, rn--; r0 -= *(*($aaaa) + rn); @endnode @node SUBI "SUBI" @{b}SUBTRACT IMMEDIATE@{ub} @{b}Addressing Mode:@{ub} Immediate @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} SUBI,r v @{b}CALM Mnemonic:@{ub} SUB r,#v SUBB r,#v @{b}Binary Code:@{ub} $A4-$A7 @{u}101001rr vvvvvvvv@{uu} 76543210 76543210 r: register (2 bits) v: value (8 bits) @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} C, CC, IDC, OVF @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This two-byte instruction causes the contents of the second byte of this instruction to be subtracted from the contents of register r. The result of the subtraction replaces the contents of register r. The subtraction is performed by taking the binary two's complement of the contents of the second instruction byte and adding that result to the contents of register r. @{b}Note:@{ub} Subtract with Borrow may be effected. See Carry (C) bit. @{b}Pseudocode:@{ub} SUBI,rn $vv ;rn -= $vv; ;2,2 @endnode @node SUBR "SUBR" @{b}SUBTRACT RELATIVE@{ub} @{b}Addressing Mode:@{ub} Relative @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} SUBR,r (*)a @{b}CALM Mnemonic:@{ub} SUB r,·+®' SUB r,\@·+®' SUBB r,·+®' SUBB r,\@·+®' @{b}Binary Code:@{ub} $A8-$AB @{u}101010rr iaaaaaaa@{uu} 76543210 76543210 r: register (2 bits) i: indirect addressing flag (1 bit) a: relative address (7 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} C, CC, IDC, OVF @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This two-byte instruction causes the contents of the byte of memory pointed to by the effective address to be subtracted from the contents of register r. The result of the subtraction replaces the contents of register r. The subtraction is performed by taking the binary two's complement of the contents of the byte of memory and adding that result to the contents of register r. Indirect addressing may be specified. @{b}Note:@{ub} Subtract with Borrow may be effected. See Carry (C) bit. @{b}Pseudocode:@{ub} SUBR,rn $aaaa ;rn -= *($aaaa); ;3,2 SUBR,rn *$aaaa ;rn -= *(*($aaaa)); ;5,2 @endnode @node SUBZ "SUBZ" @{b}SUBTRACT FROM REGISTER ZERO@{ub} @{b}Addressing Mode:@{ub} Register @{b}Size:@{ub} 1 byte @{b}Signetics Mnemonic:@{ub} SUBZ r @{b}CALM Mnemonic:@{ub} SUB A,r SUBB A,r @{b}Binary Code:@{ub} $A0-$A3 @{u}101000rr@{uu} 76543210 r: register (2 bits) @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} C, CC, IDC, OVF @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} Positive 0 1 Zero 0 0 Negative 1 0 @{b}Description:@{ub} This one-byte instruction causes the contents of the specified register, r, to be subtracted from the contents of register zero. The result of the subtraction replaces the contents of register zero. The subtraction is performed by taking the binary two's complement of the contents of register r and adding that result to the contents of register zero. The contents of register r remain unchanged. @{b}Note:@{ub} Subtract with Borrow may be effected. See Carry (C) bit. @{b}Pseudocode:@{ub} SUBZ rn ;r0 -= rn; ;2,1 @endnode @node TMI "TMI" @{b}TEST UNDER MASK IMMEDIATE@{ub} @{b}Addressing Mode:@{ub} Immediate @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} TMI,r v @{b}CALM Mnemonic:@{ub} TEST r,#n @{b}Binary Code:@{ub} $F4-$F7 @{u}111101rr vvvvvvvv@{uu} 76543210 76543210 r: register (2 bits) v: value (8 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}Register r CC1 CC0@{uu} All of the selected bits are 1s 0 0 Not all of the selected bits are 1s 1 0 @{b}Description:@{ub} This two-byte instruction tests individual bits in the specified register r to determine if they are set to binary one. During execution, each bit in the v field of the instruction is tested for a one, and if a particular bit in the v field contains a one, the corresponding bit in register r is tested for a one or zero. The condition code is set to reflect the result of the operation. If a bit in the v field is zero, the corresponding bit in register r is not tested. @{b}Pseudocode:@{ub} TMI,rn $vv ;CC = (rn & $vv == $vv) ? EQ : LT; ;3,2 @endnode @node TPSL "TPSL" @{b}TEST PROGRAM STATUS LOWER, SELECTIVE@{ub} @{b}Addressing Mode:@{ub} Immediate @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} TPSL v @{b}CALM Mnemonic:@{ub} TEST L,#n TEST CARRY TEST LOGICOMP TEST OVERFLOW TEST WITHCARRY TEST BANK or TEST BANK1 @{b}Binary Code:@{ub} $B5 @{u}10110101 vvvvvvvv@{uu} 76543210 76543210 v: value (8 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}CC1 CC0@{uu} All of the selected bits in PSL are 1s 0 0 Not all of the selected bits in PSL are 1s 1 0 @{b}Description:@{ub} This two-byte instruction tests individual bits in the Lower Program Status Byte to determine if they are set to binary one. When this instruction is executed, each bit in the v field of the second byte of this instruction is tested for the presence of a one and if a particular bit in the v field contains a one, the corresponding bit in the status byte is tested for a one or zero. The Condition Code is set to reflect the result of this operation. If a bit in the v field is zero, the corresponding bit in the status byte is not tested. @{b}Pseudocode:@{ub} TPSL $vv ;CC = (PSL & $vv == $vv) ? EQ : LT; ;3,2 @endnode @node TPSU "TPSU" @{b}TEST PROGRAM STATUS UPPER, SELECTIVE@{ub} @{b}Addressing Mode:@{ub} Immediate @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} TPSU v @{b}CALM Mnemonic:@{ub} TEST U,#n TEST IOF TEST OUTPUT TEST INPUT @{b}Binary Code:@{ub} $B4 @{u}10110100 vvvvvvvv@{uu} 76543210 76543210 v: value (8 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} CC @{b}Condition Code Setting:@{ub} @{u}CC1 CC0@{uu} All of the selected bits in PSU are 1s 0 0 Not all of the selected bits in PSU are 1s 1 0 @{b}Description:@{ub} This two-byte instruction tests individual bits in the Upper Program Status Byte to determine if they are set to binary one. When this instruction is executed, each bit in the v field of the second byte of this instruction is tested for the presence of a one and if a particular bit in the v field contains a one, the corresponding bit in the status byte is tested for a one or zero. The Condition Code is set to reflect the result of this operation. If a bit in the v field is zero, the corresponding bit in the status byte is not tested. @{b}Pseudocode:@{ub} TPSU $vv ;CC = (PSU & $vv == $vv) ? EQ : LT; ;3,2 @endnode @node WRTC "WRTC" @{b}WRITE CONTROL@{ub} @{b}Addressing Mode:@{ub} Register @{b}Size:@{ub} 1 byte @{b}Signetics Mnemonic:@{ub} WRTC,r @{b}CALM Mnemonic:@{ub} LOAD $CTRL,r @{b}Binary Code:@{ub} $B0-$B3 @{u}110100rr@{uu} 76543210 r: register (2 bits) @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} None @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This one-byte output instruction causes a byte of data to be made available to an external device. The byte to be output is taken from register r and is made available on the data bus. Signals on the busses are true levels, ie. high levels are ones. When executing this instruction, the processor raises the Operation Request (OPREQ) line and simultaneously places the data on the data bus. Along with OPREQ, the M/IO line is switched to IO, the R/W line is switched to W (Write), the D/C line is switched to C (Control), the E/NE line is switched to NE (Non-extended), and a Write Pulse (WRP) is generated. @{b}Pseudocode:@{ub} WRTC,rn ;*(CONTROLBUS) = rn; ;2,1 @endnode @node WRTD "WRTD" @{b}WRITE DATA@{ub} @{b}Addressing Mode:@{ub} Register @{b}Size:@{ub} 1 byte @{b}Signetics Mnemonic:@{ub} WRTD,r @{b}CALM Mnemonic:@{ub} LOAD $DATA,r @{b}Binary Code:@{ub} $F0-$F3 @{u}111100rr@{uu} 76543210 r: register (2 bits) @{b}Execution Time:@{ub} 2 cycles (6 clock periods) @{b}Processor Registers Affected:@{ub} None @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This one-byte output instruction causes a byte of data to be made available to an external device. The byte to be output is taken from register r and is made available on the data bus. Signals on the busses are true levels, ie. high levels are ones. When executing this instruction, the processor raises the Operation Request (OPREQ) line and simultaneously places the data on the data bus. Along with OPREQ, the M/IO line is switched to IO, the R/W line is switched to W (Write), and a Write Pulse (WRP) is generated. Also, during the valid OPREQ signals, the D/C line is switched to D (Data) and the E/NE line is switched to NE (Non-extended). @{b}Pseudocode:@{ub} WRTD,rn ;*(DATABUS) = rn; ;2,1 @endnode @node WRTE "WRTE" @{b}WRITE EXTENDED@{ub} @{b}Addressing Mode:@{ub} Immediate @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} WRTE,r v @{b}CALM Mnemonic:@{ub} LOAD $n,r @{b}Binary Code:@{ub} $D4-$D7 @{u}110101rr vvvvvvvv@{uu} 76543210 76543210 r: register (2 bits) v: value (8 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} None @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This two-byte output instruction causes a byte of data to be made available to an external device. The byte to be output is taken from register r and is made available on the data bus. Simultaneously, the data in the second byte of this instruction is made available on the address bus. The second byte, v, may be interpreted as a device address. Signals on the busses are true levels, ie. high levels are ones. When executing this instruction, the processor raises the Operation Request (OPREQ) line and simultaneously places the data from register r on the data bus and the data from the second byte of this instruction on the address bus. Along with OPREQ, the M/IO line is switched to IO, the R/W line is switched to W (Write), the E/NE line is switched to E (Extended), and a Write Pulse (WRP) is generated. @{b}Pseudocode:@{ub} WRTE,rn $vv ;*(ADDRESSBUS) = $vv; *(DATABUS) = rn; ;3,2 @endnode @node ZBRR "ZBRR" @{b}ZERO BRANCH, RELATIVE@{ub} @{b}Addressing Mode:@{ub} Relative @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} ZBRR (*)a @{b}CALM Mnemonic:@{ub} JUMP 0+® JUMP \@0+® @{b}Binary Code:@{ub} $9B @{u}10011011 iaaaaaaa@{uu} 76543210 76543210 i: indirect addressing flag (1 bit) r: relative address (7 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} None @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This two-byte unconditional relative branch instruction directs the processor to calculate the effective address differently than the usual calculation for the Relative Addressing mode. The specified value, a, is interpreted as a relative displacement from page zero, byte zero. Therefore, displacement may be specified from -64 to +63 bytes. The address calculation is modulo 8192, so the negative displacement actually will develop addresses at the end of page zero. For example, ZBRR -8 will develop an effective address of 8184, and ZBRR +52 will develop an effective address of 52. This instruction causes the processor to clear address bits #13 and #14, the page address bits, and to replace the contents of the Instruction Address Register (IAR) with the effective address of the instruction. This instruction may be executed anywhere within addressable memory. Indirect addressing may be specified. @{b}Pseudocode:@{ub} ZBRR $aaaa ;goto $aaaa; ;3,2 ZBRR *$aaaa ;goto *($aaaa); ;5,2 @endnode @node ZBSR "ZBSR" @{b}ZERO BRANCH TO SUBROUTINE, RELATIVE@{ub} @{b}Addressing Mode:@{ub} Relative @{b}Size:@{ub} 2 bytes @{b}Signetics Mnemonic:@{ub} ZBSR (*)a @{b}CALM Mnemonic:@{ub} CALL 0+® CALL \@0+® @{b}Binary Code:@{ub} $BB @{u}10111011 iaaaaaaa@{uu} 76543210 76543210 i: indirect addressing flag (1 bit) r: relative address (7 bits) @{b}Execution Time:@{ub} 3 cycles (9 clock periods) @{b}Processor Registers Affected:@{ub} SP @{b}Condition Code Setting:@{ub} N/A @{b}Description:@{ub} This two-byte unconditional relative subroutine branch instruction directs the processor to calculate the effective address differently than the usual calculation for the Relative Addressing mode. The specified value, a, is interpreted as a relative displacement from page zero, byte zero. Therefore, displacement may be specified from -64 to +63 bytes. The address calculation is modulo 8192, so the negative displacement actually will develop addresses at the end of page zero. For example, ZBRR -8 will develop an effective address of 8184, and ZBRR +52 will develop an effective address of 52. This instruction causes the processor to clear address bits #13 and #14, the page address bits, and may be executed anywhere within addressable memory. Indirect addressing may be specified. When executed, this instruction causes the Stack Pointer (SP) to be incremented by one, the address of the byte following this instruction is pushed into the Return Address Stack (RAS), and control is transferred to the effective address. @{b}Pseudocode:@{ub} ZBSR $aaaa ;gosub $aaaa; ;3,2 ZBSR *$aaaa ;gosub *($aaaa); ;5,2 @endnode @node AppC "C: INSTRUCTIONS, ADDITIONAL INFORMATION" The 2650 uses variable length instructions that are one, two or three bytes long. The instruction length is determined by the nature of the operation being performed and the addressing mode being used. Thus, the instruction can be expressed in one byte where no memory operand addressing is necessary, as with register-to-register or rotate instructions. On the other hand, for direct addressing instructions, three bytes are allocated. The relative and immediate addressing modes allow two-byte instructions to be implemented. The 2650 uses explicit operand addressing; that is, each instruction species the operand address. The first byte of each 2650 instruction is divided into three fields and specified the operation to be performed, the addressing mode to be used and, where appropriate, the register or condition code mask to be used. @{u}fffcccrr@{uu} 76543210 f: function field (3 bits) c: class field (3 bits) r: register field (2 bits) The class field species the instruction group, the major address mode and the number of processor cycles required for each instruction. The class field also specifies, with one exception, the number of bytes in the instruction. The following table shows the specifications for each class. Class Instruction Address Byte Direct @{u}Field Group Register Length Cycles@{uu} 0 Arithmetic Register 1 2 1 Arithmetic Immediate 2 2 2 Arithmetic Relative 2 3 3 Arithmetic Absolute 3 4 4 Control (incl. rotate) Various 1 2 5 Control Various 1-2 3 6 Branch Relative 2 3 7 Branch Absolute 3 3 Within the arithmetic group (classes 0, 1, 2 and 3), the function field specifies one of the eight operations as follows: Function Arithmetic @{u}Field Operation@{uu} 0 Load 1 Exclusive OR 2 AND 3 Inclusive OR 4 Add 5 Subtract 6 Store 7 Compare Within the branch group (classes 6 and 7), the function field specifies one of the eight operations as follows: Function Branch @{u}Field Operation@{uu} 0 Branch on Condition True 1 Branch to Subroutine on Condition True 2 Branch on Register Non-Zero 3 Branch to Subroutine on Register Non-Zero 4 Branch on Condition False 5 Branch to Subroutine on Condition False 6 Branch on Incrementing Register 7 Branch on Decrementing Register There is very little pattern to the use of the function field within the control group (classes 4 and 5). The register field is used to specify the index register, to specify the operand source register, to specify the destination register, or a condition code mask. For the register-to-register and the indexed instructions, register zero is implicitly assumed to be the source or the destination for the instruction. For all other instructions that involve a register, the register field allows any of four registers to be specified, except for indexed branch instructions which require that register 3 be specified. Conditional branch instructions utilize the 2-bit register field as a condition code mask field. A few instructions use the register field as part of the operation code and consequently allow no variation in register usage. @endnode @node AppE "E: SUMMARY OF 2650 INSTRUCTION MNEMONICS" In these tables parentheses are used to indicate options. In no case are they coded in any instruction. The following abbreviations are used: r - register expression, must evaluate to 0 <= r <= 3. v - value expression * - indirect indicator a - address expression x - index register expression X - index register expression with optional auto-increment or auto- decrement NOTES: - the use of the indirect indicator is always optional. - when an index register expression is specified, it can be followed by ',+' or ',-' which indicates use of auto-increment or auto- decrement of the index register. For example: LODA,r0 DPR,r3,+ @{"BXA" link BXA} and @{"BSXA" link BSXA} are exceptions and do not permit auto-increment or auto-decrement. - even though an address expression is specified in a hardware relative addressing instruction, the assembler develops it into a value of (-64 <= V <= +63). - a memory reference instruction which requires indexing may use only register zero as the destination of the operation. - if an index register expression is used with either the @{"BXA" link BXA} or @{"BSXA" link BSXA} instructions it must specify index register #3 (either register bank) for indexing. Any other value in the index field will produce an error during assembly. However, it is not necessary to use an index register expression with these instructions; a blank in this field will default to register #3. LOAD/STORE 1 @{"LODZ" link LODZ} r Load Register Zero 2 @{"LODI" link LODI},r v Load Immediate 2 @{"LODR" link LODR},r (*)a Load Relative 3 @{"LODA" link LODA},r (*)a(,X) Load Absolute 1 @{"STRZ" link STRZ} r Store Register Zero 2 @{"STRR" link STRR},r (*)a Store Relative 3 @{"STRA" link STRA},r (*)a(,X) Store Absolute ARITHMETIC 1 @{"ADDZ" link ADDZ} r Add to Register Zero 2 @{"ADDI" link ADDI},r v Add Immediate 2 @{"ADDR" link ADDR},r (*)a Add Relative 3 @{"ADDA" link ADDA},r (*)a(,X) Add Absolute 1 @{"SUBZ" link SUBZ} r Subtract from Register Zero 2 @{"SUBI" link SUBI},r v Subtract Immediate 2 @{"SUBR" link SUBR},r (*)a Subtract Relative 3 @{"SUBA" link SUBA},r (*)a(,X) Subtract Absolute LOGICAL 1 @{"IORZ" link IORZ} r Inclusive OR to Register Zero 2 @{"IORI" link IORI},r v Inclusive OR Immediate 2 @{"IORR" link IORR},r (*)a Inclusive OR Relative 3 @{"IORA" link IORA},r (*)a(,X) Inclusive OR Absolute 1 @{"EORZ" link EORZ} r Exclusive OR to Register Zero 2 @{"EORI" link EORI},r v Exclusive OR Immediate 2 @{"EORR" link EORR},r (*)a Exclusive OR Relative 3 @{"EORA" link EORA},r (*)a(,X) Exclusive OR Absolute 1 @{"ANDZ" link ANDZ} r AND to Register Zero 2 @{"ANDI" link ANDI},r v AND Immediate 2 @{"ANDR" link ANDR},r (*)a AND Relative 3 @{"ANDA" link ANDA},r (*)a(,X) AND Absolute BRANCH 2 @{"BCTR" link BCTR},v (*)a Branch on Condition True Relative 2 @{"BCTA" link BCTA},v (*)a Branch on Condition False Relative 3 @{"BCFR" link BCFR},v (*)a Branch on Condition True Absolute 3 @{"BCFA" link BCFA},v (*)a Branch on Condition False Absolute 2 @{"BRNR" link BRNR},r (*)a Branch on Register Non-Zero Relative 3 @{"BRNA" link BRNA},r (*)a Branch on Register Non-Zero Absolute 2 @{"BIRR" link BIRR},r (*)a Branch on Incrementing Register Relative 3 @{"BIRA" link BIRA},r (*)a Branch on Incrementing Register Absolute 2 @{"BDRR" link BDRR},r (*)a Branch on Decrementing Register Relative 3 @{"BDRA" link BDRA},r (*)a Branch on Decrementing Register Absolute 3 @{"BXA " link BXA } (*)a(,x) Branch Indexed, Absolute 2 @{"ZBRR" link ZBRR} (*)a Zero Branch, Relative SUBROUTINE BRANCH 2 @{"BSTR" link BSTR},v (*)a Branch to Subroutine on Condition True, Relative 3 @{"BSTA" link BSTA},v (*)a Branch to Subroutine on Condition True, Absolute 2 @{"BSFR" link BSFR},v (*)a Branch to Subroutine on Condition False, Relative 3 @{"BSFA" link BSFA},v (*)a Branch to Subroutine on Condition False, Absolute 2 @{"BSNR" link BSNR},r (*)a Branch to Subroutine on Non-Zero Register, Relative 3 @{"BSNA" link BSNA},r (*)a Branch to Subroutine on Non-Zero Register, Absolute 3 @{"BSXA" link BSXA} (*)a(,x) Branch to Subroutine Indexed, Absolute 2 @{"ZBSR" link ZBSR} (*)a Zero Branch to Subroutine, Relative SUBROUTINE RETURN 1 @{"RETC" link RETC},v Return from Subroutine, Conditional 1 @{"RETE" link RETE},v Return from Subroutine and Enable Interrupt, Conditional COMPARISON 1 @{"COMZ" link COMZ} r Compare to Register Zero 2 @{"COMI" link COMI},r v Compare Immediate 2 @{"COMR" link COMR},r (*)a Compare Relative 3 @{"COMA" link COMA},r (*)a(,X) Compare Absolute INPUT/OUTPUT 1 @{"REDC" link REDC},r Read Control 1 @{"REDD" link REDD},r Read Data 1 @{"WRTC" link WRTC},r Write Control 1 @{"WRTD" link WRTD},r Write Data 2 @{"REDE" link REDE},r v Read Extended 2 @{"WRTE" link WRTE},r v Write Extended PROGRAM STATUS MANIPULATION 1 @{"LPSU" link LPSU} Load Program Status, Upper from r0 1 @{"LPSL" link LPSL} Load Program Status, Lower from r0 3 @{"LDPL" link LDPL} (*)a Load Program Status, Lower from memory 1 @{"SPSU" link SPSU} Store Program Status, Upper to r0 1 @{"SPSL" link SPSL} Store Program Status, Lower to r0 3 @{"STPL" link STPL} (*)a Store Program Status, Lower to memory 2 @{"CPSU" link CPSU} v Clear Program Status, Upper 2 @{"CPSL" link CPSL} v Clear Program Status, Lower 2 @{"PPSU" link PPSU} v Preset Program Status, Upper 2 @{"PPSL" link PPSL} v Preset Program Status, Lower 2 @{"TPSU" link TPSU} v Test Program Status, Upper 2 @{"TPSL" link TPSL} v Test Program Status, Lower ROTATE 1 @{"RRR " link RRR },r Rotate Register Right 1 @{"RRL " link RRL },r Rotate Register Left MISCELLANEOUS 1 @{"NOP " link NOP } No Operation 1 @{"HALT" link HALT} Halt, Enter Wait State 2 @{"TMI " link TMI },r v Test Under Mask Immediate 1 @{"DAR " link DAR },r Decimal Adjust Register @endnode @node AppF "F: NOTES ABOUT THE 2650 PROCESSOR" 1. Auto-increment, decrement of index register: This feature is optional on any instruction which uses indexing with the exception of @{"BXA" link BXA} and @{"BSXA" link BSXA}. The increment or decrement occurs before the index register is added to the displacement in the instruction. 2. The contents of registers when used for indexing are considered to be unsigned absolute numbers. Consequently, index registers can contain values from 0 to 255. They "wrap-around" so that the number following 255 is 0. 3. Only absolute addressing instructions can be indexed. 4. The @{"BDRA" link BDRA}, @{"BDRR" link BDRR}, @{"BIRA" link BIRA} and @{"BIRR" link BIRR} instructions perform the increment or decrement before testing for zero. The only time the branch is not taken is when the register contains zero. 5. All hardware relative addressing is implemented as modulo 8K and therefore relative addressing across the top of a page boundary will result in a physical address near the bottom of the page being accessed. For example: $1FFC LODR,r2 $+16 This instruction results, during execution, in accessing the byte at location $000C in the same page as the instruction. Similarly, negative relative addresses from near the bottom of a page may result in an effective address near the top of the page. 6. Page boundaries cannot be indexed across. 7. Data can always be accessed across a page boundary through use of relative indirect or absolute indirect addressing modes. 8. The only way to transfer control to a program in some other page is to branch absolute or branch indirectly to the new page. Program execution cannot flow across a page boundary. 9. Unconditional branch or branch to subroutine instructions are coded by specifying a value of 3 in the register/value field of @{"BSTA" link BSTA}, @{"BSTR" link BSTR}, @{"BCTA" link BCTA} or @{"BCTR" link BCTR}. For example: UN EQU 3 ... ... ... BSTA,un PAL BCTR,r3 LOOP Unconditional branches on conditions false (@{"BCFA" link BCFA}, @{"BCFR" link BCFR}) are not allowed. @endnode