Signetics PIP 2650 Architektur

    Computermuseum der Fakultät Informatik                          german

## `Architecture of the PIP 2650`

    Registers of the 2650:
                7 6 5 4 3 2 1 0
              :-----------------:
              :      R0         :
              :-----------------:
      7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0
    :-----------------:  :-----------------:  :-----------------:
    :      R1         :  :      R1'        :  :     PSWU        :----:
    :-----------------:  :-----------------:  :-----------------:    :
    :      R2         :  :      R2'        :  :     PSWL        :    :
    :-----------------:  :-----------------:  :-----------------:    :
    :      R3         :  :      R3'        :                         :
    :-----------------:  :-----------------:                         :
                                                                     :
             4 3 2 1 0 9 8 7 6 5 4 3 2 1 0                           :
           :----:--------------------------:                         :
           :    :       IAR   13 Bit       :                         :
           :----:--------------------------:                         :
           :-------------------------------:                         :
           :                               :                         :
           :      IAR-Stack                :<------------------------:
           :      8 * 15 Bit               :
           :                               :
           :-------------------------------:

    R0 is the accumulator, R1 to R3 are common 8Bit registers.
    There are two register sets: Rx and Rx'. By a bit loaded to the PSWL
    register, you can switch between the two different register sets.
    This makes possible a fast reaction time for the interrupt processing.
    The program count IAR("Instruction Adress Register") consists
    of two parts: the lower 13Bit are incremented on each program step.
    The 2 upper Bits are not incremented. Thus the memory adressing space
    is divided into 4 pages with each 8192Bit.
    The 16th adressing bit used for indirect adressing like at other
    minicomputers(for example hp2100).
    On subroutine calls, the state of the IAR is stored on an 8 word
    hardwarestack, which is integrated to one of the chips. This increases
    indeed the reaction time for interrupts, where also the simple
    possibility to switch the register set belongs to, but however is a
    hard limit, that can't be avoided and that doesn't make possible the
    extension of hard- and software behind a certain barrier in any way.
    That's why microprocessors with such restrictions became extincted
    very soon.

`back to the cmputermuseum`