------------------------------------------------ PAGE 1 -------------------- UNDERSTANDING THE MICROPROCESSOR MICRORPCOESSORS DOLPHIN UNDERSTANDING SYSTEM JD Nicoud TABLE OF CONTENTS Part I: Introduction to the DOLPHIN 1. Introduction 2 2. Microprocessor system 2 3. Program 3 4. Running the Program 4 5. Signal processor 5 6. Signal memory 5 7. Signals and interfaces 7 8. Program interface and simplified 7 9. Waiting loops 8 Part II: Programming the processor Signetics / Philips 2650 1. Introduction 9 2. Internal registers of 2650 9 3. Transfer instructions between registers and memory 10 4. Instructions for initializing the registers 12 5. Transfer instructions between registers and peripherals 12 6. Complement to 1 and February 12 7. Relative addressing 14 8. Addressing state 16 9. Mode register 17 10. Arithmetic operations of addition 17 11. Subtraction 19 12. Logical Operations 23 13. Shift Operations 24 14. Operations increment and decrement 25 15. Comparison operations and test 25 16. Jump instructions 26 17. Countdown with 30 jump 18. Call subroutine 31 19. Various instructions 33 20. Indexed addressing 34 21. Indirection 37 22. Indexed addressing indirectly 38 23. Special Instructions / O 39 24. Interrupt 39 Appendices: Mnemo-nic tables 20-21 Signetics conversion - mnemo 40-nics June 1977 edition dexième January 1978 PAGE 2 ------------------------------------------------ -------------------- UNDERSTANDING THE MICROPROCESSOR Part I: INTRODUCTION TO SYSTEM DAUPHIN 1. INTRODUCTION The objective of AC booklet is to provide simple explanation correct on all aspects of microprocessors in order to allow start all those who find the original documentation of Manufacturers indigestible. Examples illustrating system programming and its DAUPHIN Signetics 2650 processor, but with the notation used, different from Signetics, it is in fact the concepts core microprocessors that appear in these examples. We will try to use technical terms French, indicating their English equivalent between two slashes. The knowledge of English is essential in this area if wants lon access to records of the manufacturers. 2. MICROPROCESSOR SYSTEM We must distinguish between a microprocessor and a system microprocessor. The microprocessor is generally reduced to a unit arithmetic and control, its structure will be discussed later. A microprocessor system includes, in addition to the processor, memory and interface input / output, depending on the application. The memory contains the program and data and can be reading and writing (RAM) !RAM: Random Access Memory! or Read only (ROM) !ROM: Read Only Memory!. Recall that memory is a set of numbered boxes. The number is called !Address! and the word is called content, data, content, information, code !data!. The content is a binary word of 8 bits in general. It is nice to have the program in a ROM (we say often: in ROM) to avoid the charge of each enclenchment the device. The data on which the program operates, shall by cons to be in RAM for the program to change them. The simple system of Fig. 1 controls a loudspeaker or a lamp. The type of memory is ROM or RAM, which contains the program. The interface which controls the loudspeaker is equivalent to having a memory and an address where you can write only one bit. If this bit is 0, the speaker is at rest (lamp off). If this bit is 1, the membrane of the loudspeaker is drawn (lamp lit). For the high- speaker, so it's a change from state 0 to 1 or 1 to 0 will create noise. [Fig. 1: System microprocessor controlling a loudspeaker.] PAGE 3 ------------------------------------------------ -------------------- The processor contains at least three registers: the program counter !PC: Program Counter Point address of the memory location containing instruction to execute. The instruction register !instruction Register !instruction stores during its execution. The Register Battery !A: Accumulator! is used for transfers and arithmetic operations. There are usually other registers the arithmetic unit and will be explained later. The processor, memory and interface are connected by lines control bus called !bus!. A distinction is usually the address bus, who help carry the contents of memory locations and registers devices, and control lines that synchronize transfers. The details of the control signals will be seen later. 3. PROGRAM The program stored in memory corresponds to the succession of orders give the processor so that it performs correctly and transfer operations between its registers, memory and peripherals. The program to oscillate the membrane of our speaker (or flash lamp) is as follows: HP = 74; value of the constants used by the program HPOF = 0 HPON = 1 . LOC 0; start address of program Oscil: LOAD A, # HPOF HP $ LOAD, A; released membrane LOAD A, # HPON HP $ LOAD, A; membrane drawn JUMP Oscil The first two instructions transfer a 0 in the registry HP. This 0 must first be loaded into the accumulator (the instruction for writing a direcctement any value in memory or in an interface does not exist because the limited number of instructions in a microprocessor). By analyzing more closely the first two lines of the program, see the label first Oscil: it is a name given to the first program instruction. This name corresponds to an address, so a number, but the exact location of the program in memory does not interested at this time. It is clearer to refer to names, abbreviated symbols that evoke the function performed, we speaks of symbolic addressing. the statement following the first label is symbolic LOAD A, # HPOF. This means that the register A processor is responsible "Load" with the value given in the statement HPOF (known value immediate). The # sign is pronounced "value" and states that we want load a numeric value contained in the statement (value immediately), not the contents of a memory location whose address is given in the statement. HPOF is zero, as stated initially. It might seem easier to write LOAD A, # 0, but this does not show as clearly the intent of the programmer. In addition, if the interface changes as clearly not the intention of the programmer. Moreover, if the interface changes (addition of an amplifier inverter for example) to a different value is that we must put in instruction and is easier to correct the value once program began as plotôt get into the program all instructions which act on the speaker. The following statement LOAD $HP,A load device address HP by the contents of A. The dollar sign ($) is pronounced "peripheral" and describes it as a device address, not a memory address. Again, a name was given at the Device (symbolic address). The digital PAGE 4 ------------------------------------------------ -------------------- value associated with that name is declared at the beginning of the program. The following two statements are the same type and set output interface with the state (membrane drawn, lamp lit). The program ends with a jump instruction !Jump! to the instruction whose address is given in symbolic form: Oscil whose value is 0. When this program is executed, the oscillation frequency of speaker depends on the speed of the processor. We shall see how to improve this program to make the oscillation frequency adjustable independently of the processor. 4. ENFORCEMENT PROGRAM When the program is loaded into memory (for switches grace or control to a special program loading), the execution can begin. A reset signal is required on each processor to initialize the search and make the first instruction, usually at 0. In this case, if our little program is only in memory, it must start at 0, which is specified by the pseudo-instruction . LOC 0 (instruction for the program or the person performing the binary translation program). The first phase of the investigation is looking! Fetch! of instruction itself. The address counter PC site content on the address bus and selects the corresponding word in memory. The Content is transferred by the data bus into the register instruction (Fig. 2a). In the second phase of this first statement, decoding circuitry of the processor recognizes that it is a a statement charging the accumulator and immediate exéctutent ! Execute! transfer value in A (Fig. 2b). Simultaneously, the instruction counter PC is increased by 1 (increment). A new instruction cycle will therefore seek the instruction code to address 1 (Fig. 2c). The decoding of this instruction tells the processor it is a transfer to a device. Address device, which is part of the instruction is placed on the address bus, a control signal to the appropriate sélectrionne device and not memory, and the value contained in A is transferred to the register of the selected device (Fig. 2d). A nouveau the program address counter is increased to the next instruction. The two statements that follow are of a type known to pass the 5th instruction, which is first tramsférée (Fig. 2e) before being recognized as an unconditional jump. In this case, the address of the jump is transferred into the address counter (PC), instead of incrementing usual (Fig. 2f). The following statement will be searched Cetta address. The above explanations do not take into account the constraints imposed by the binary encoding instructions, immediate values, addresses devices and jump addresses in memory. It was assumed that each instruction corresponds to a single memory word. In microprocessors today, words of 8 bits are used value Cetta is a common compromise between performance, even better than the word is long, and the price depends on opportunities for integration in a minimum number of integrated circuits. It is in this case coding instructions using one, two or three (Four in the Z80) consecutive memory words. The above program, coded for the 2650, looks like this: [Listing] PAGE 5 ------------------------------------------------ -------------------- [Listing (cont.)] We note that the addresses are numbered in octal, not decimal. The same content are octal. The system used is binary. The octal and hexadecimal notations are used as condensed binary. One advantage of the octal ia binary conversion is faster, and that transactions are more easy (10 110 011 = 263, 127 + 34 = 163). Decimal numbers followed by a period to avoid confusion (26. = 32). Running the program for 2650 is in the same sequence, but several transfers (cycles) !cycles! are required for each instruction. Each cycle can itself take several pulses clock, the processor must pass through a succession of states !States! to effect a transfer (leave address, select the memory or peripheral effector transfer, increment the PC). When the program is carried out step by step !Step! during the preparation point, which can be three types of step: state by state !State step!, Cycle by cycle !Step cycle! or instruction by instruction !Step instruction!. One can also imagine no greater if appropriate decoding circuits are implemented. 5. SIGNAL PROCESSOR As already mentioned, the processor must receive a control signal to be booted, reset !reset!. It must then select the memory device or devices for reading !read! or writing !write!. Each processor uses both signals different, which can be reduced with a simple logic to the following signals. ADMEM (M): Select a memory address ADPER (P): Selection of a device address WRITE (W): Indicates that a write is performed. For various reasons, the signals are switched on bus and called ADMEMLOW, WRITELOW RESETLOW and to show that they are assets to the state zero down !low!. For example, for a reading memory, you must WRITE = 0, the corresponding lamp is turned off, but WRITELOW bus = 1. The concept of literacy is tojours on the processor. The other signals and interface structure with 2650 will be seen later. 6. MEMORY SIGNALS A memory is selected above by the signal ADMEM; if WRITE = 0, contents of the memory address is read selected above! read! and appears on the data bus. If WRITE = 1, the state data bus is transferred into the memory location whose address is on the bus address. The address must naturally correspond to an address existing. The memory size is limited and occupies only part of possible addresses. The detailed diagram of a memory 128. words of 8. bits DAUPHIN compatible is given in Fig. 3. This memory responds to addresses 0 to 177 (octal): it is easy verify that when the addresses 2^7 - 2^11 ($80..$7FF) are 0, the AND gate selection circuit !CS: Chip Select! is in state 1. PAGE 6 ------------------------------------------------ -------------------- [Fig. 2. Sequences of program implementation of paragraph 4.] PAGE 7 ------------------------------------------------ -------------------- [Fig. 3. Detailed diagram of a memory 6810.] 7. SIGNALS AND INTERFACES Devices are selected by Adper, read or writing by the value of WRITE. There are special circuit interface device, but for simple applications, some TTL circuits LS series !Low Schottky Power! solve the problem to better conditions. For example, the interface compatible speakerphone with the previous program is given in Fig. 4. The decoder to address uses a 74LS138 circuit and decodes the addresses 64, 65, 66, 67 (octal naturally) in reading and writing. Only 6 bits address are decoded, allowing a maximum of 64. peripherals, addresses 0 to 77. If the device 64 is selected for writing, the flip-flop receives at the end of the ADPER pulse a rising edge active in flip-flop that stores the state of corresponding bus line (line of low weight, so the value 1 or 0 binary word transferred by bus). [Fig. 4. Speaker interface compatible with the program of § 4.] 8. PROGRAM INTERFACES AND SIMPLIFIED The same problem can be solved in countless ways, both view programming !software! that the material point of view !hardware!. For example, the program can be written given Initially due PAGE 8 ------------------------------------------------ -------------------- [Listing] The program takes up less space in memory where the instructions and CLR INC. have no numerical value associated and are shorter (8 bits). Both training exist however in this form on 2650. The disadvantage of this new program is that the flip-flop of the interface speaker can be plugged into the LSB. Greater simplification of the program can be obtained with interface Fig. 5, used in DOLPHIN. [Fig. 5. Speaker interface implemented in the DAUPHIN.] Device selection switch 6 is a divider by two, independently of the word on the data bus, and both read in writing. The program then reads: [Listing] 9. Wait loop Oscil previous programs provide ultrasonic speed rated processor. A few training runs microseconds, and the above program gives a frequency of 34. kHz. To reduce the frequency, you must insert a wait loop, made with a counter that counts. A second register of the processor can utilitisé be for it. A conditional jump instruction goes back to count the register as the resulting is not equal !NE: not EQUAL! zero. [Listing] PAGE 9 ------------------------------------------------ -------------------- Assuming, for simplicity, that all previous instructions last 5 mu.s, a half-period lasts 5 +5 + DELAY. (5 +5) +5, 15 + DELAY.10 microseconds. For a normal LA 432 Hz, we must set DELAY = 115. (Decimal). The corresponding value is 161 octal as 113. = 1.x64. + 6.x8. + 1. As DELAY is less than 377 = 255. There is no problem. For larger delays, we must use such two loops using two nested counting meters. The above program is valid for the Intel 8080 and Motorola for the 6800. With the Signetics 2650, a single instruction replaces decrement and conditional jump. We can write the following program, given with its equivalent octal ready loaded and executed in a DAUPHIN: [Listing] Note immediately that this program can be encoded differently using the relative addressing mode available in 2650 and explained in Part II. [The rest of page 9, and pages 10 .. 38] PAGE 39----------- ------------------------------------- ------------------- 23. SPECIAL INSTRUCTIONS FOR INPUT-OUTPUT Four instructions were provided in 2650 for the selection of 4 Preferred devices, decoded from address bits 2 ^ 13 and 2 ^ 14. These instructions do not apply in Dolphin, as it does not incorporate decoding circuitry to take advantage of these instructions. It can however achieve the demonstration program DAUPHIN simpler: remove the memory plate, put on ADFLOT (Free address), WRITE with 60 and the word RUN. The processor executes instruction 60 (LOAD A,$CTRL), is to tell the device which reads the address is in the address counter. All devices are selected and the address lights flash. 24. INTERRUPTION When an interrupt request by the line / INTREQ Processor (Active at state 0), if the processor was in the state ION (Interrupt it), it runs at the end of the current instruction not the following statement, but a call instruction subroutine, the subroutine is called in this case interrupt routine. Internally, the code 273 (0 + CALL ® ') is forced into the instruction register and the processor reads on the bus the second byte of this instruction by generating a negative pulse / INTACK !interrupt Acknowledge!. The device requesting the interrupt is sensible INTACK recognize the leadership and place on the bus address of the interrupt routine (or the address of the location that contains address this routine if indirect addressing is used), this address lies between 0 and 77 or 0 and -100 (1777700). 2650 DAUPHIN plate leads to 2 sockets signals / INTREQ (IR) and / INTACK (AI) For experiments can bind / INTREQ at OV to an interrupt request, and link / INTACK to socket / Writer finding the switch to WRITE (leave this switch DAFLOT). When / INTACK is active, the state switches DATA is read and Simply place the interrupt vector to see how processor interpreter. At the time of the interruption, the processor will automatically IOF !Interrupt off!. Upon return from the interrupt routine, it must General resensitizing processor interruptions. The instruction RETION simulans can return to the interruption and continue the program developed and recover interrupted by ION. Proper management of interruptions poses several difficult problems. In particular, do not forget to save the state of all registers used by the interrupt routine, including U and L, if we want to continue running correctly after the service interruption. To overcome some shortcomings of this routine Rescue Signetics plans to add new instructions in the 2650-B, which will be best used in applications with interruption. The programming experience is acquired largely by studying programs written by other people. These are not always models, because people with becoup experience are rare, but there tojours qulque good idea to pick up. ELEclub the journal clubs and electronic GESO Microclub (club followers of the microprocessor), regularly publishes examples of Dolphin programs, To subscribe, contact Writing ELEclub, Prilly 3 rd, 1008 Lausanne, Switzerland. To get also examples of programs supplied by Signetics (AS52: General Delay routines; AS50 Input / Output; AS53: Binary Arithmetic routines; AS54: Conversion routines; Save and Restore Interrupt Routine Using The 2650A; AS55 Decimal Fixed Point Arithmetic), the list given last page makes the conversion. [Page 40] END OF DOCUMENT ----------------------------------------------- ------------